Dynamic Memory Power Allocation via Interleaving Patterns
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Solution Overview
Problem
Image capture devices, such as cameras, face challenges in managing power consumption due to the high demand of volatile memory for image processing, which affects battery life.
Innovation Solution
Implementing dynamic power allocation for memory using multiple interleaving patterns, where a memory management circuitry translates virtual addresses into physical addresses using different interleaving patterns to optimize memory usage and power conservation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If volatile memory is used for image processing, then processing capability is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic power allocation by allowing the memory management circuitry to switch between different interleaving patterns (first and second patterns) based on operational mode. This dynamic switching enables the system to adjust memory access patterns and power distribution in real-time, optimizing the balance between processing capability and power consumption without requiring device reboots.
2Quantity of substance
If multiple memory devices are used, then memory capacity and bandwidth are improved, but power consumption increases
Solution Approach 1:
The patent divides the set of memory devices into a first subset and a second subset, which are then selectively powered down based on operational requirements. This segmentation allows the system to activate only the necessary portion of memory devices for a given task, reducing overall power consumption while maintaining adequate memory capacity and bandwidth when needed.
Solution Approach 2:
The patent applies different interleaving patterns that selectively map virtual addresses to different subsets of memory devices. By controlling which memory devices are accessed based on the specific operational mode, the system optimizes power consumption locally across different memory devices while maintaining overall system performance.
3Use of energy by moving object
If dynamic mode switching is implemented, then power consumption is reduced, but system complexity increases
Solution Approach 1:
The patent introduces a memory management circuitry as an intermediary component that handles the complexity of mode switching and interleaving pattern translation. This dedicated circuitry manages the mapping between virtual addresses and physical memory devices, abstracting the complexity from the rest of the system while enabling dynamic power allocation through different interleaving patterns.
Data Source
AI summary
Systems and methods are disclosed for dynamic power allocation for memory using multiple interleaving patterns. For example, a system may include a set of memory devices, including a first subset and a second subset, and a memory management circuitry configured to translate virtual addresses into physical addresses of memory locations in the set of memory devices using a first interleaving pattern when operating in a first mode; and translate virtual addresses using a second interleaving pattern when operating in a second mode. The first and second interleaving patterns both map virtual addresses in a first range exclusively to memory devices in the first subset. The first interleaving pattern maps virtual addresses in a second range to memory devices in the first subset and in the second subset. The second interleaving pattern maps virtual addresses in the second range exclusively to memory devices in the first subset.