Dynamic Memory Power Gating via Content Addressable Memory
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Solution Overview
Problem
Semiconductor-based logic devices face significant power consumption due to leakage currents, especially when idle, and existing solutions like state retention power gating (SRPG) incur area overhead and require large dedicated memory and fast buses for data transfer.
Innovation Solution
An information processing device with a controller that dynamically selects specific volatile memory units to power down based on runtime requests, using data transfer circuitry and power gating circuitry, allowing for adaptive reduced power mode entry and exit without special flip-flops or additional area impact, and enabling dynamic redefinition of memory units to power down.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If state retention power gating (SRPG) is used to reduce leakage current, then power consumption is reduced, but area overhead increases by about 10% due to special flip-flops and additional power grids
Solution Approach 1:
The patent uses a content addressable memory (CAM) to store the content of flip-flops instead of using special SRPG flip-flops. The CAM acts as a copy of the flip-flop data, allowing power gating without requiring modified flip-flop structures. This eliminates the area overhead associated with special SRPG flip-flops while maintaining the power reduction benefit.
Solution Approach 2:
The patent employs a universal power gating mechanism that can be applied to any flip-flop in the design without requiring design-specific modifications. The CAM-based approach provides a general solution that works across different flip-flop types and designs, eliminating the need for area-consuming special-purpose SRPG flip-flops while maintaining compatibility with existing designs.
2Use of energy by moving object
If large amounts of data are transferred from all flip-flops to enable power gating, then power consumption is reduced, but large dedicated memory and fast buses are required
Solution Approach 1:
The patent uses a content addressable memory (CAM) to store the content of flip-flops instead of using special SRPG flip-flops. The CAM acts as a copy of the flip-flop data, allowing power gating without requiring modified flip-flop structures. This eliminates the area overhead associated with special SRPG flip-flops while maintaining the power reduction benefit.
Solution Approach 2:
The patent dynamically selects which memory units to power down based on runtime requests and current operational state. The controller evaluates which specific memory units can be safely powered off and only transfers data for those units, rather than transferring data from all flip-flops. This dynamic approach reduces the amount of data transfer required and eliminates the need for large dedicated memory and fast buses.
3Use of energy by moving object
If volatile memory is powered off to save energy, then power consumption is reduced, but data must be transferred to and from low-power memory
Solution Approach 1:
The patent pre-loads the content of flip-flops into the CAM before power gating occurs. This preliminary action ensures that data is already available in the CAM when power gating is initiated, eliminating the need for data transfer during the power state transition. The CAM maintains the flip-flop data in a ready state, allowing immediate restoration without transfer delays.
Solution Approach 2:
The CAM acts as an intermediary between the flip-flops and the rest of the system during power gating. Instead of directly transferring data between flip-flops and main memory, the CAM serves as a buffer that holds flip-flop data, allowing the flip-flops to be powered off without requiring immediate data transfer. This intermediary structure reduces the time penalty associated with data transfer.
Data Source
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AI summary
An information processing device (10) comprises a first memory (12), a second memory (14), data transfer circuitry (22), power gating circuitry (18), and a controller (20). The first memory comprises at least two volatile memory units (16). The controller (20) receives or generates a request for setting the information processing device (10) into a reduced power mode; in response to the request, it selects specific memory units (24) among the memory units (16); controls the data transfer circuitry (22) to transfer data from the selected memory units (24) to the second memory (14); and controls the power gating circuitry (18) to power down the selected memory units (24).