Dynamic Memory Power Management via DRAM-NVRAM Switching
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Solution Overview
Problem
Memory systems in electronic devices consume excessive power even when not actively accessed, as components are kept continuously powered to maintain quick response times, which is inefficient for applications where power conservation is crucial.
Innovation Solution
Implementing a memory controller that dynamically manages power by evaluating performance demands and switching between volatile DRAM and non-volatile NVRAM, powering down DRAM banks when performance requirements are met by NVRAM to conserve energy, while ensuring system performance is maintained.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If volatile memory (DRAM) is continuously powered to maintain quick response times, then memory access speed is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic power management by transitioning DRAM banks between active and power-down states based on real-time performance demands. The memory controller monitors access patterns and dynamically adjusts power states, allowing the system to adapt between high-performance and low-power modes rather than maintaining a static power level.
Solution Approach 2:
The system employs periodic monitoring of memory access patterns and performance demands to determine when to transition DRAM banks between active and power-down states. This periodic evaluation enables the system to cyclically adjust power consumption while maintaining performance when needed.
2Use of energy by moving object
If power domain switches are used to deactivate components for power saving, then power consumption is reduced, but additional power is required to drive the switches
Solution Approach 1:
The patent divides the memory system into separate power domains for DRAM and NVRAM, allowing independent power management of each segment. This segmentation enables the system to power down entire DRAM banks when not needed, rather than using switches within a unified power domain, thereby reducing the overhead associated with power switching.
3Speed
If volatile memory is used for fast access, then memory performance is improved, but data is lost when power is disconnected
Solution Approach 1:
The patent introduces NVRAM as an intermediary layer between the host and DRAM. The memory controller acts as a mediator that manages data placement between volatile and non-volatile memory, ensuring that data requiring persistence is stored in NVRAM while allowing fast access to frequently used data in DRAM.
Solution Approach 2:
The system performs preliminary actions by pre-fetching data from NVRAM to DRAM before it is needed and proactively writing back data from DRAM to NVRAM before power-down events. This preliminary data movement ensures that performance is maintained when DRAM is active and data safety is ensured before power transitions.
4Use of energy by moving object
If non-volatile memory is used to service requests, then power consumption is reduced, but access speed decreases
Solution Approach 1:
The patent applies local quality by allowing different memory regions to have different characteristics - DRAM provides high-speed access for active data while NVRAM provides power-efficient storage for less frequently accessed data. The memory controller intelligently directs access requests to the appropriate memory type based on data usage patterns and performance requirements.
Data Source
AI summary
Systems, methods, and apparatus related to a memory system that manages an interface for a volatile memory device and a non-volatile memory device to control memory system power. In one approach, a controller evaluates a demand on memory performance. If the demand of a current computation task needed by the host is high, a DRAM device is powered-up to meet the demand. Otherwise, if the non-volatile memory device is adequate to meet the demand, the DRAM memory is partially or fully-powered down to save power. In another approach, a task performed for a host device uses one or more resources of a first memory device (e.g., DRAM). A performance capability of a second memory device (e.g., NVRAM) is determined. A controller of the memory system determines whether the performance capability of the second memory device is adequate to service the task. In response to determining that the performance capability is adequate, the controller changes a mode of operation of the memory system so that one or more resources of the second memory device are used to service the task.