Dynamic Memory Prefetching for Low-Frequency Power Reduction
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Solution Overview
Problem
Existing prefetching approaches in processor architectures often degrade performance and increase DC power consumption, particularly when processors operate at lower clock frequencies.
Innovation Solution
Implement dynamic prefetching mechanisms that enable or disable cache prefetch based on a comparison of processor clock frequency with a settable threshold, using secure monitor calls and exception level registers to manage prefetch values dynamically.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If prefetching is enabled to improve processing throughput, then processing latency is reduced, but DC power consumption increases
Solution Approach 1:
The patent implements dynamic prefetching control by transitioning from static to dynamic operation modes. The system dynamically adjusts prefetcher behavior based on real-time clock frequency measurements, enabling prefetching when beneficial and disabling it when harmful, thus resolving the contradiction between throughput improvement and power consumption
Solution Approach 2:
The system changes the operational parameter of the prefetcher based on clock frequency comparisons. When clock frequency exceeds a threshold, the prefetcher is enabled; when below the threshold, it is disabled. This parameter change allows the system to adapt prefetching behavior to current processing conditions, balancing performance and power consumption
2Use of energy by moving object
If static prefetcher disabling is used to reduce power consumption, then DC power consumption decreases, but processing engine performance degrades
Solution Approach 1:
The patent replaces static disabling with dynamic control mechanisms. Instead of permanently disabling the prefetcher to save power, the system dynamically enables or disables prefetching based on real-time clock frequency measurements, maintaining performance when needed while reducing power consumption when appropriate
Solution Approach 2:
The system implements feedback control by continuously monitoring clock frequency and using this information to adjust prefetcher operation. The feedback loop ensures that prefetching is activated only when processing conditions justify the performance benefit, avoiding the performance degradation associated with static disabling
3Loss of time
If prefetching is enabled at all times to maintain performance, then processing latency is minimized, but DC power consumption increases unnecessarily
Solution Approach 1:
The system employs periodic evaluation of clock frequency against threshold values to determine prefetcher operation. This periodic assessment allows the system to maintain low latency when processing demands justify prefetching while avoiding unnecessary power consumption during periods when prefetching would be harmful
Solution Approach 2:
The patent changes the operational state of the prefetcher based on clock frequency parameter comparisons. By adjusting the prefetcher's enable/disable state according to real-time frequency measurements, the system optimizes the balance between maintaining minimal latency and reducing power consumption
Data Source
AI summary
Aspects of the disclosure are directed to dynamic memory prefetching. In accordance with one aspect, the disclosure includes a main memory configured to store data; a memory hierarchy coupled to the main memory, the memory hierarchy configured to augment the main memory; and a trusted zone element coupled to the memory hierarchy, the trusted zone element configured to read a shared memory to determine a specific control register and one or more prefetch values based on a secure monitor call (SMC). In another aspect, the disclosure includes reading a shared memory to determine a specific control register and one or more prefetch values based on a secure monitor call (SMC); and writing the one or more prefetch values to an exception level register.