Dynamic Memory Redundancy With Priority Decoding
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Solution Overview
Problem
Existing memory subsystem designs face challenges in efficiently addressing process variations during fabrication, leading to bit cell failures in SRAM-based memory systems, as the redundancy logic area grows proportionally with memory size, consuming valuable area and power.
Innovation Solution
A dynamic memory redundancy scheme with priority decoding is implemented, which dynamically repairs local IO units based on redundancy fuse input patterns and generates redundancy shift signals to shift lower order IO units, reducing the need for extensive routing and decoding logic, thereby saving area and power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional static redundancy schemes are used to address process variations and bit cell failures, then reliability is improved, but device complexity and area consumption increase proportionally with memory size
Solution Approach 1:
The patent implements dynamic redundancy by using multiplexers to selectively activate different redundancy fuse banks based on the detected defect location. Instead of static redundancy logic that remains active for all memory operations, the system dynamically configures which redundancy bank is active, reducing the effective redundancy logic area needed at any given time while maintaining comprehensive coverage for bit cell failures
Solution Approach 2:
The redundancy system is divided into multiple independent fuse banks (first redundancy fuse bank and second redundancy fuse bank), each capable of independently repairing different memory banks. This segmentation allows the redundancy logic to be distributed and activated selectively, reducing the complexity of any single redundancy logic unit while maintaining overall system reliability
2Reliability
If extensive routing and decoding logic is implemented to achieve comprehensive redundancy coverage, then reliability is improved, but area consumption increases
Solution Approach 1:
The patent merges the redundancy decoding logic into the existing global IO controller structure, utilizing the same routing infrastructure for both normal memory operations and redundancy activation. By combining redundancy control functions with existing IO control logic, the patent eliminates the need for separate extensive routing and decoding logic, achieving comprehensive redundancy coverage while minimizing additional area consumption
Solution Approach 2:
The global IO controller is designed to perform multiple functions: normal memory access control and redundancy activation. The same control signals and routing paths are used for both operational modes, making the system multi-functional and eliminating the need for dedicated redundancy-specific routing and decoding logic, thereby saving memory area
3Reliability
If more redundancy fuse level shifters and global redundancy signals are added to expand redundancy capacity, then reliability is improved, but power consumption and area increase
Solution Approach 1:
The system uses periodic or selective activation of redundancy fuse banks based on the detected defect pattern. Instead of continuously activating all redundancy signals, the system selectively enables only the necessary redundancy bank during each memory operation, reducing power consumption while maintaining the capacity to handle various failure scenarios. The multiplexer dynamically switches between redundancy banks based on operational needs
Data Source
AI summary
A method for a memory subsystem redundancy with priority decoding is described. The method includes dynamically repairing a local input/output (IO) unit of a first memory subsystem bank based on a current redundancy fuse input pattern of the first memory subsystem bank. The method also includes concurrently generating a redundancy shift signal in each global IO based on the current redundancy fuse input pattern to shift the repaired local IO unit and lower order local IO units of the first memory subsystem bank relative to the repaired local IO unit.