Dynamic Memory Refresh Control for Leakage Mitigation
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Solution Overview
Problem
Dynamic Random Access Memory (DRAM) faces challenges in achieving high-density storage due to its 1T1C structure, which is not suitable for three-dimensional stacking, and new memory technologies like the 1S1C unit struggle with capacitor leakage affecting read and write operations.
Innovation Solution
A method for operating dynamic memory with two-terminal gate devices connected in series, involving wordlines and bitlines, where refresh operations are performed at predetermined intervals to maintain capacitor voltage, ensuring accurate read and write operations by temporarily storing data and rewriting it after each read operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If refresh operations are performed at predetermined intervals to maintain capacitor voltage, then read and write accuracy is improved, but system complexity and operation overhead increase
Solution Approach 1:
The patent implements periodic refresh operations at predetermined intervals to restore capacitor voltage before it drops below the critical threshold. This periodic maintenance action ensures data accuracy without requiring continuous intervention, balancing reliability with operational efficiency.
Solution Approach 2:
The system performs preliminary checks of operation commands to determine whether refresh operations are needed before executing read or write operations. By anticipating and preparing for potential voltage degradation, the system maintains data integrity proactively rather than reactively.
2Reliability
If capacitor voltage is maintained through frequent refresh operations, then data reliability is improved, but time for actual data operations is reduced
Solution Approach 1:
Refresh operations are performed periodically at optimized intervals rather than continuously, maintaining data reliability while minimizing interference with normal read and write operations. The periodic timing is calibrated to prevent excessive refresh frequency from consuming operational time.
Solution Approach 2:
The system skips unnecessary refresh operations by intelligently determining when capacitor voltage remains above the critical threshold. When voltage is sufficient, refresh operations are skipped, allowing data operations to proceed without interruption and reducing overall operation time.
3Measurement precision
If the interval time T is reduced to prevent voltage drop, then read operation accuracy is improved, but the frequency of refresh operations increases
Solution Approach 1:
The system performs preliminary assessment of capacitor voltage status and operation command types to determine the appropriate refresh timing. By evaluating the actual need for refresh before executing operations, the system avoids unnecessary frequent refreshes while maintaining read accuracy.
Solution Approach 2:
The refresh interval parameter T is dynamically adjusted based on operational conditions and voltage degradation rates. Rather than using a fixed conservative interval that would increase refresh frequency, the system adapts the timing parameter to match actual memory cell characteristics and usage patterns.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively prevents read and write errors caused by capacitor leakage, ensuring reliable data retrieval and storage in dynamic memory cells, even during voltage drops, thereby enhancing storage density and operational stability.
Implementation Method 1
Each memory cell includes a capacitor and a two-terminal gate device connected in series
Implementation Method 2
The two-terminal gate device has bidirectional conduction characteristics and has a conduction threshold voltage VTH
Implementation Method 3
the charge stored in the capacitor will be gradually lost due to the leakage effect
Data Source
AI summary
A method for operating a dynamic memory is provided, and the method includes the following steps. A refresh operation is performed on the dynamic memory according to predetermined interval time T, an operation command is received in real time at the same time, a read operation is performed on a selected memory cell according to position information of the selected memory cell in the operation command when the operation command is received, and state data read in the read operation is temporarily stored in a read buffer. The interval time T is less than time t required for a voltage value of a capacitor in the memory cell to drop to a critical capacitor voltage value for the read operation to correctly read the state data of the memory cell during a write operation. According to operation command type information in the operation command, corresponding operations are performed on the selected memory cell.