Dynamic Memory Reliability Configuration via Controller
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Solution Overview
Problem
Conventional computing devices are limited by a fixed reliability scheme tied to their hardware configuration, which cannot be changed after deployment, making it difficult to adapt to varying memory error requirements across different processes, and reducing memory capacity due to error detection and correction techniques.
Innovation Solution
A memory controller that dynamically selects and implements different reliability schemes, such as ECC, parity, or data mirroring, on a per-process or per-page basis, decoupling the operating memory from the reliability scheme, allowing for flexible configuration and partitioning of memory regions with varying reliability levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional fixed reliability schemes are used, then hardware configuration is simple, but adaptability to different process requirements is poor
Solution Approach 1:
The patent implements dynamic reliability schemes where the memory controller can change reliability configurations at runtime based on process requirements. The system transitions from static hardware-bound reliability to dynamic software-configurable reliability, allowing the same physical memory to serve different reliability needs through configuration changes rather than hardware modifications.
Solution Approach 2:
The memory controller is designed to support multiple reliability schemes (ECC, parity, mirroring, no protection) within a single device. This universal controller can adapt its behavior based on the requirements of different processes, making one hardware component serve multiple reliability functions that previously required different hardware configurations.
2Reliability
If error detection and correction techniques are applied to all memory, then reliability is improved, but memory capacity is reduced
Solution Approach 1:
The patent applies different reliability schemes to different memory regions or allocations based on the specific requirements of each process. Critical processes receive high-reliability schemes like ECC or mirroring, while non-critical processes use simpler schemes or no protection, optimizing the balance between reliability and capacity for each local memory usage scenario.
Solution Approach 2:
Instead of applying full error protection to all memory, the system applies partial protection only where necessary. The memory controller can selectively enable reliability schemes for specific processes or memory regions, providing adequate protection for critical data while preserving maximum capacity for non-critical storage needs.
3Reliability
If strong error protection is applied, then memory reliability is improved, but memory utilization is reduced
Solution Approach 1:
The system changes the reliability parameter dynamically based on process requirements. By adjusting the level of protection (from no protection to full ECC) according to the criticality of each process, the system optimizes both reliability and utilization, ensuring that memory resources are adequately protected when needed while remaining fully available when protection is unnecessary.
4Adaptability or versatility
If hardware configuration determines reliability scheme, then device complexity is low, but flexibility after deployment is poor
Solution Approach 1:
The patent introduces a software layer or configuration interface that mediates between the hardware memory controller and the reliability requirements of processes. This intermediary allows reliability schemes to be configured and changed without modifying hardware, enabling flexible adaptation while keeping the hardware controller's complexity manageable through standardized interfaces.
Data Source
AI summary
Technology relating to configurable reliability schemes for memory devices is disclosed. The technology includes a memory controller that selectively controls at least a type or an extent of a reliability scheme for at least a portion of a memory device. The technology also includes a computing device that can dynamically select and employ reliability schemes from a collection of different reliability schemes. A reliability scheme may be selected on a per-process, per-allocation request, per-page, per-cache-line, or other basis. The reliability schemes may include use of parity, use of data mirroring, use of an error correction code (ECC), storage of data without redundancy, etc.