Dynamic Memory Relocation Mechanism for Active Logical Partitions
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Solution Overview
Problem
In computing systems, main memory associated with active logical partitions cannot be relocated between physical partitions without disrupting the system, leading to suboptimal resource allocation over time due to limited dynamic allocation and de-allocation capabilities.
Innovation Solution
A dynamic memory relocation mechanism that moves data within the main memory of a multi-level cache subsystem without interrupting processing, allowing for defragmentation and physical affinity optimization of active logical partitions by disabling memory operations at the source and enabling node controllers to handle memory operations at the target location.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If main memory is relocated between physical partitions for active logical partitions, then resource allocation optimality is improved, but system disruption occurs requiring suspension of the partition or entire system
Solution Approach 1:
The patent segments the memory relocation process into discrete storage increments that can be moved independently. Each storage increment is a manageable unit that can be relocated without affecting the entire memory space, allowing the system to perform partial relocations while maintaining partition operation continuity.
Solution Approach 2:
The patent implements dynamic memory relocation where storage increments can be moved between physical partitions while the logical partition remains active. The system dynamically adjusts memory mappings and redirects access paths during relocation, eliminating the need for static suspension and enabling continuous operation during resource optimization.
2Reliability
If main memory cannot be relocated without disruption, then system stability is maintained, but optimal resource allocation over time is not obtained
Solution Approach 1:
The patent performs preliminary actions by creating and maintaining a mapping structure that tracks the physical locations of storage increments before relocation occurs. This mapping information is prepared in advance and used during relocation to ensure continuous access, allowing the system to stabilize memory references before actual movement happens.
Solution Approach 2:
The patent introduces an intermediary mapping mechanism that mediates between the logical partition's memory views and the physical storage locations. This intermediary layer translates and redirects memory access requests during relocation, maintaining system stability while enabling efficient resource allocation through seamless storage increment movement.
3Reliability
If traditional memory relocation methods are used, then system disruption is avoided, but relocation speed is slow and resource reallocation is inefficient
Solution Approach 1:
The patent applies partial action by relocating only the necessary storage increments rather than moving entire memory spaces. This selective approach enables faster relocation speeds by processing smaller units of data, while maintaining continuous operation through parallel processing of multiple storage increments without disrupting the logical partition.
Data Source
AI summary
A computing device is provided and includes a plurality of nodes. Each node includes multiple chips and a node controller at which the multiple chips are assignable to logical partitions. Each of the multiple chips includes processors and a memory unit configured to handle local memory operations originating from the processors. The node controller includes a dynamic memory relocation (DMR) mechanism configured to move data having a DMR storage increment address relative to a local one of the memory units without interrupting a processing of the data by at least one of the logical partitions. During movement of the data by the DMR mechanism, the memory units are disabled from handling the local memory operations matching the DMR storage increment address and the node controller handles the local memory operations matching the DMR storage increment address.