Dynamic Memory Block Status Checking via Staged Read Tests
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Solution Overview
Problem
Existing memory systems face challenges in efficiently managing and maintaining the operational status of nonvolatile memory blocks, leading to performance degradation and increased read disturb issues, which affect data reliability and storage efficiency.
Innovation Solution
A method and apparatus that dynamically determine the operation status of memory blocks by performing read test operations in stages, adjusting the number of word lines based on error detection, and implementing read reclaim and wear leveling operations to reduce errors and improve data reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If read test operations are performed frequently to check memory block status, then reliability of data storage is improved, but read disturb increases and performance degrades
Solution Approach 1:
The patent implements dynamic status checking by adjusting the frequency and scope of read test operations based on the operational state of memory blocks. The controller monitors error rates and operational status in real-time, then dynamically modifies checking intensity - performing comprehensive checks on blocks with high error rates while reducing or skipping checks on blocks with low error rates, thus resolving the contradiction between reliability monitoring and read disturb minimization
Solution Approach 2:
The patent changes the parameters of read test operations based on detected error rates and memory block status. When error rates are high, the system increases checking frequency and expands the scope of read tests. When error rates are low, the system reduces checking frequency and scope. This parameter adaptation allows the system to maintain data reliability while minimizing unnecessary read operations that cause read disturb
2Measurement precision
If comprehensive read test operations are performed on all memory blocks, then measurement precision of operation status is improved, but loss of time increases
Solution Approach 1:
The patent segments the memory device into multiple memory blocks and further divides read test operations into selective stages. Instead of uniformly testing all blocks, the controller prioritizes specific blocks based on error rate monitoring and operational status. This segmentation allows the system to achieve precise status measurement of critical blocks while skipping less critical blocks, thereby reducing overall checking time while maintaining measurement precision where needed
Solution Approach 2:
The patent applies partial action by performing read test operations only on memory blocks that require monitoring based on their operational status and error rates. The controller identifies and targets specific blocks for comprehensive testing while omitting blocks with stable operation. This partial approach provides sufficient measurement precision for blocks that matter most while significantly reducing the time required compared to comprehensive testing of all blocks
3Duration of action of stationary object
If wear leveling operations are performed frequently to distribute write cycles, then durability of memory device is improved, but productivity decreases due to additional operations
Solution Approach 1:
The patent implements feedback-based wear leveling where the controller continuously monitors operational status and error rates of memory blocks. Based on this feedback, the system dynamically adjusts wear leveling operations - performing them more frequently on blocks showing signs of degradation or uneven wear, and reducing or skipping them on blocks with uniform, healthy operation. This feedback mechanism ensures durability is maintained through targeted wear leveling while minimizing the productivity impact of excessive operations
Solution Approach 2:
The patent changes the frequency and scope of wear leveling operations based on monitored parameters such as error rates, operational status, and write cycle distribution. When parameters indicate uneven wear or approaching failure thresholds, the system increases wear leveling activity. When parameters show uniform, healthy operation, the system reduces wear leveling frequency. This parameter-driven adaptation balances durability maintenance with productivity preservation
Data Source
AI summary
A memory system includes a memory device including a plurality of memory blocks, each including a plurality of memory cells coupled to a plurality of word lines, and a controller configured to determine an operation status regarding a selected memory block among the plurality of memory blocks by performing read test operations to the selected memory block in stages. During the read test operations, the controller adjusts the numbers of word lines selected in each of the stages, based on an error.