Dynamic Memory Tester for Real-World Temperature and Voltage Screening
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor testers are limited to testing either volatile or non-volatile memories, lack the ability to replicate end-user conditions, and cannot perform real-world functional tests under varying temperatures and voltages, leading to inadequate prediction of end-user needs and memory failures.
Innovation Solution
A dynamic memory tester unit with a Master Controller Unit (MCU) that manages Slave Controller Units (SCUs) to perform parallel testing of both volatile and non-volatile memories, capable of reconfiguring voltage levels, frequencies, and temperatures to mimic end-user environments and run real-time test patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If generic semiconductor testers are used to test memories, then testing can be performed with fixed functional test patterns, but the testers cannot replicate end-user conditions or predict end-user failures
Solution Approach 1:
The testing system dynamically adjusts operational parameters including voltage levels, frequency rates, and temperature conditions to replicate various end-user environments. The system transitions from static fixed-pattern testing to dynamic adaptive testing that mimics real-world usage scenarios, enabling prediction of end-user failures under different operational conditions.
2Ease of manufacture
If fixed functional test patterns are used, then testing is simplified and standardized, but real-world functional tests under varying conditions cannot be performed
Solution Approach 1:
The system implements variable voltage levels, frequency rates, and temperature conditions to create multiple test scenarios. By changing these parameters, the system maintains standardized testing procedures while accurately replicating diverse end-user environmental conditions, thus achieving both simplicity and precision.
3Reliability
If separate testers are used for volatile and non-volatile memories, then each tester can be optimized for specific memory types, but testing efficiency and resource utilization decrease
Solution Approach 1:
The testing system is designed as a universal platform capable of testing both volatile and non-volatile memory types within the same system. The system maintains specialized testing capabilities for different memory types while consolidating resources, thereby improving testing efficiency and resource utilization without compromising testing accuracy.
4Reliability
If rigorous testing is performed to ensure reliability, then memory components meet quality standards, but testing time and cost increase
Solution Approach 1:
The system performs preliminary testing under normalized conditions to quickly identify obviously defective units, then applies more rigorous stress testing only to units that pass initial screening. This staged approach maintains high reliability standards while reducing overall testing time by avoiding exhaustive testing of all units with the same intensity.
Data Source
AI summary
A memory testing device uses a master control unit to concurrently operate multiple, intelligent, slave control units (SCUs). SCUs have one or more processing unit(s) (i.e. Finite State Machines, micro controllers, processors) capable of processing one or more firmware with or without operating system (i.e. bare-metal, embedded OS, RTOS (real time operating system)) to perform a series of task defined by firmware(s) for testing volatile and/or non-volatile memory devices connected into one or more DUT devices plus SCU has capability of having operating system and install and run host applications locally within each SCU units to mimic host applications environments along with performing regular memory testing.