Dynamic Memory Throughput Control for Shared DRAM Systems
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Solution Overview
Problem
Conventional priority schemes for electronic devices with shared memory, such as DRAM, can limit memory access for some components unnecessarily, reducing efficiency and throughput, especially during periods of low memory load.
Innovation Solution
An electronic device with a shared DRAM system that allows data processing circuits to dynamically adjust their data throughput based on the access load of the DRAM, using a communication bus and local controllers to receive controlling signals, thereby optimizing memory access and reducing unnecessary limitations on initiators.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional priority scheme is used to grant DRAM access to multiple initiators, then guaranteed throughput is achieved for each initiator, but memory access efficiency is reduced due to unnecessary limiting of initiators during low load periods
Solution Approach 1:
The patent implements dynamic throughput adjustment where the data processor can vary its memory access rate based on system conditions. The controller monitors memory access patterns and adjusts the throughput dynamically - allowing higher throughput when memory load is low and reducing throughput when memory is congested, thereby resolving the contradiction between guaranteed throughput and memory access efficiency
Solution Approach 2:
The patent changes the throughput parameter adaptively based on memory access load conditions. By monitoring metrics such as memory queue depth or access patterns, the system modifies the data throughput parameter to match actual demand, enabling the system to achieve both guaranteed throughput during normal operation and high memory efficiency during low load periods
2Reliability
If buffers within initiators are enlarged to compensate for memory access inefficiency, then data processing reliability is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent introduces a feedback mechanism where the data processor provides information about its memory access needs and actual throughput performance to the controller. This feedback loop enables the controller to adjust memory access granting dynamically, reducing the need for large buffers in initiators while maintaining data processing reliability through intelligent coordination rather than over-provisioning
3Productivity
If initiators are limited to maintain average memory access bandwidth, then system performance is guaranteed, but access locality is reduced due to frequent memory page switching
Solution Approach 1:
The patent implements preliminary actions by allowing initiators to accumulate data in smaller buffers during low-load periods before memory access is needed. This anticipatory data gathering reduces the frequency of memory page switching during critical operations, as data is already prepared in local buffers, thereby reducing the loss of time to memory page switching while maintaining system performance guarantees
Data Source
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AI summary
The invention relates to an electronic device (100) comprising: a memory (103) configured to be accessed by at least one data processing circuit (101), wherein the memory (103) is associated with an access load. The at least one data processing circuit (101) is allocated a data throughput for accessing the memory (103) is configured to be controlled to adjust a data throughput on the basis of the access load of the memory (103) and the respective data throughput. Moreover, the invention relates to a corresponding method.