Dynamic Memory Timing Parameter Adjustment
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Solution Overview
Problem
Current memory devices use fixed timing parameters, leading to idle data bus time when accessing data from the same row, reducing data bus throughput for sequential requests.
Innovation Solution
Dynamic timing parameters are determined based on column access latency to optimize data bus utilization by modifying the timing parameters based on memory access requests, reducing idle time when accessing data from the same row.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If fixed timing parameters are used for memory access, then timing parameter stability is improved, but data bus throughput deteriorates due to idle cycles when accessing sequential data in the same row
Solution Approach 1:
The patent applies dynamics by transitioning from fixed timing parameters to dynamic timing parameters that adapt based on memory access patterns. Specifically, the system determines whether sequential memory accesses target the same row and adjusts the timing parameter (RL value) accordingly - using a reduced value when accessing the same row and a standard value when accessing different rows, thereby optimizing data bus utilization while maintaining operational stability
Solution Approach 2:
The patent implements parameter changes by modifying the timing parameter (read-to-data latency) based on the specific access pattern detected. The system changes the RL parameter value dynamically: when sequential accesses are detected within the same row, a reduced timing parameter is applied to eliminate idle cycles; when accessing different rows, the standard timing parameter is maintained, thus improving throughput without compromising reliability
2Device complexity
If fixed timing parameters are used for all memory accesses, then device complexity is reduced, but loss of time increases due to unnecessary idle data bus cycles
Solution Approach 1:
The patent applies self-service by implementing an automatic detection and adjustment mechanism within the memory system. The system autonomously monitors memory access patterns, identifies sequential accesses to the same row, and dynamically adjusts timing parameters without requiring external intervention or complex external control logic, thereby reducing time loss while maintaining manageable device complexity
Solution Approach 2:
The patent implements feedback by creating a closed-loop system that monitors memory access requests, detects patterns (specifically sequential accesses to the same row), and uses this information to adjust timing parameters dynamically. This feedback mechanism enables the system to eliminate unnecessary idle cycles automatically, reducing time loss without proportionally increasing device complexity
Data Source
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AI summary
A particular method includes receiving, from a processor, a first memory access request at a memory device. The method also includes processing the first memory access request based on a timing parameter of the memory device. The method further includes receiving, from the processor, a second memory access request at the memory device. The method also includes modifying a timing parameter of the memory device based on addresses identified by the first memory access request and the second memory access request to produce a modified timing parameter. The method further includes processing the second memory access request based on the modified timing parameter.