Dynamic Memory Timing Parameter Selection

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Solution Overview

Problem

Traditional methods for communicating with memory devices in portable systems often use a single set of timing parameters set by manufacturers, which can be slower than the devices' capabilities, leading to inefficient data transfer and increased space requirements in controllers due to large tables of parameters.

Innovation Solution

A computational system and method where a controller dynamically selects timing parameters from a table ordered by speed, adjusting based on error rates to use faster or slower sets as needed, eliminating duplicate entries and optimizing communication with memory devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a large table with 50 to 100 timing parameter entries is used to cover all possible devices, then all devices can be supported, but the controller occupies excess space

Engineering Contradiction:
Improvedevice compatibilityVSAvoidcontroller size
Core Design Contradiction:
Adaptability or versatilityVSVolume of stationary object

Solution Approach 1:

The patent extracts only the essential timing parameter sets needed for operation from the large comprehensive table. By identifying and removing redundant duplicate entries, the solution maintains device compatibility while significantly reducing the controller's memory footprint. The controller keeps only the minimum necessary timing parameter configurations rather than storing all possible device-specific variations.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent implements a universal timing parameter set that can be applied to multiple different memory devices regardless of their specific manufacturer or model. This multi-functional approach allows a single timing parameter configuration to serve various devices, eliminating the need for extensive device-specific entries in the controller's table.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Device complexity

If a single set of timing parameters is used for all devices, then controller complexity is reduced, but data transfer speed is limited to the slowest device's rate

Engineering Contradiction:
Improvecontroller complexityVSAvoiddata transfer rate
Core Design Contradiction:
Device complexityVSSpeed

Solution Approach 1:

The patent implements a dynamic timing parameter selection mechanism that automatically adjusts the timing parameters based on the specific memory device being accessed. Rather than using a static single set of parameters, the controller dynamically selects from multiple predefined timing parameter sets, allowing optimization of data transfer speed for each device while maintaining manageable controller complexity through automated selection logic.

Inventive Principle:
Principle #15Dynamics

3Reliability

If manufacturer-specified timing parameters are used, then device reliability is ensured, but data transfer operates at slower rates than devices are capable of

Engineering Contradiction:
Improvecommunication reliabilityVSAvoiddata transfer efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent changes the timing parameters from the conservative manufacturer-specified values to optimized values that are faster but still reliable. By implementing a systematic approach to test and validate faster timing parameters, the solution transitions from using slow, guaranteed-safe parameters to using faster parameters that have been empirically verified to work correctly, thereby improving productivity while maintaining reliability.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS7685333B2Method and system for communicating with memory devices utilizing selected timing parameters from a timing table
Publication Date: 2010.03.23 NXP USA INC
  • US7685333B2 patent drawing
  • US7685333B2 patent drawing
  • US7685333B2 patent drawing

AI summary

A computational system is disclosed. The computational system includes a controller having a table including a plurality of sets of timing parameters. The plurality of sets of timing parameters are ordered based on a speed rate. The computational system also includes a device accessible to the controller. The controller communicates with the device in accordance with one set of timing parameters selected from the plurality of sets of timing parameters.