Dynamic Multilevel Memory Configuration for Workload Adaptation
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Solution Overview
Problem
Existing memory systems statically configure between single level memory (1LM) and two level memory (2LM) architectures at boot time, failing to adapt to varying system workloads, which can negatively impact performance.
Innovation Solution
A system that dynamically configures 1LM and 2LM regions during runtime, allowing the operating system to select between memory space configurations based on workload performance characteristics, enabling migration of memory pages between near and far memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If memory configuration is set statically at boot time, then system simplicity is maintained, but system performance deteriorates when workload does not match the selected configuration
Solution Approach 1:
The patent implements dynamic memory configuration by allowing the operating system to switch between 1LM and 2LM modes at runtime based on workload characteristics. The BIOS pre-configures both modes, and the OS selects the appropriate configuration dynamically, transforming the static memory system into a dynamic one that adapts to different operational requirements.
Solution Approach 2:
The system changes the memory configuration parameter (1LM vs 2LM mode) based on workload demands. The BIOS prepares both configurations with different parameter settings, and the OS adjusts the active configuration parameter according to performance requirements, enabling the system to optimize for different workload types.
2Speed
If 1LM configuration is selected, then memory access speed is improved for small workloads, but memory capacity utilization deteriorates for large workloads
Solution Approach 1:
The system dynamically switches between 1LM and 2LM configurations based on workload size and characteristics. For small workloads, it operates in 1LM mode for fast access; for large workloads, it transitions to 2LM mode to utilize full memory capacity, thereby adapting to different workload requirements.
Solution Approach 2:
The memory system is designed to perform multiple functions by supporting both 1LM and 2LM configurations. The BIOS pre-configures both modes, enabling the system to universally handle different workload types - small workloads benefit from 1LM speed while large workloads utilize 2LM capacity.
3Quantity of substance
If 2LM configuration is selected, then memory capacity is maximized, but cache thrashing increases for small workloads
Solution Approach 1:
The system dynamically adjusts the memory configuration based on workload size. For small workloads, it switches to 1LM mode to avoid cache thrashing and maintain high efficiency. For large workloads requiring maximum capacity, it transitions to 2LM mode, thereby optimizing system efficiency across different workload scenarios.
Solution Approach 2:
The OS changes the memory configuration parameter between 1LM and 2LM modes based on workload analysis. This parameter change allows the system to maximize capacity when needed (2LM mode) while maintaining efficiency for smaller workloads (1LM mode), preventing cache thrashing.
4Adaptability or versatility
If dynamic configuration is implemented, then workload adaptability is improved, but system complexity increases
Solution Approach 1:
The BIOS performs preliminary action by pre-configuring both 1LM and 2LM modes before the OS starts. This advance preparation eliminates the need for complex runtime configuration decisions, as the OS only needs to select between pre-prepared configurations, thereby reducing the actual runtime complexity despite enhanced adaptability.
Solution Approach 2:
The BIOS acts as an intermediary that prepares both memory configurations in advance. This intermediary layer handles the complexity of dual configuration setup, allowing the OS to simply choose between pre-configured modes without dealing with the underlying complexity of memory configuration management.
Data Source
AI summary
A system can dynamically migrate memory pages from near memory to far memory during runtime. A system basic input output system (BIOS) can program a first memory address space of size P and a second memory address space of size P to a near memory (NM) space of size (N) and a far memory (FM) space of size (M), where P equals N+M. For the first memory address space, the OS can manage the NM space and the FM space as a flat memory space with an address space of size P available. For the second memory address space, the OS can manage the NM space as a NM cache for FM, with an address space of size M available.