Dynamic Memory Write Policy Translation for SSD Performance

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Solution Overview

Problem

Modern Managed NAND systems and SSDs face challenges in efficiently writing and programming TLC and QLC NAND pages, as existing techniques either write one page at a time or change the data layout across different dice, leading to inefficiencies in read performance, SRAM resource usage, and padding requirements.

Innovation Solution

The proposed solution dynamically adjusts the write policy based on host throughput and write performance needs, switching between die-fast and channel-fast programming approaches during a single programming sequence to optimize memory operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If die-fast programming is used to improve write speed, then write throughput is improved, but read performance deteriorates

Engineering Contradiction:
Improvewrite throughputVSAvoidread speed
Core Design Contradiction:
ProductivityVSSpeed

Solution Approach 1:

The patent implements dynamic write policy selection that adapts between die-fast and channel-fast programming modes based on real-time performance needs. The system monitors workload characteristics and automatically switches programming strategies, allowing optimal read performance when needed while maintaining high write throughput when appropriate.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the programming parameter (write policy) between die-fast and channel-fast modes depending on performance requirements. This parameter switching allows the system to optimize for either write speed or read performance based on current workload characteristics without being locked into a single programming mode.

Inventive Principle:
Principle #35Parameter changes

2Speed

If channel-fast programming is used to improve read performance, then read speed is improved, but write throughput deteriorates

Engineering Contradiction:
Improveread speedVSAvoidwrite throughput
Core Design Contradiction:
SpeedVSProductivity

Solution Approach 1:

The system dynamically selects between channel-fast and die-fast programming modes based on real-time performance monitoring. When read performance becomes the priority, the system switches to channel-fast mode, and when write throughput is more important, it transitions to die-fast mode, allowing flexible adaptation to changing workload requirements.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The write policy parameter is dynamically changed between channel-fast and die-fast modes based on performance needs. This allows the system to optimize read performance when necessary while maintaining the ability to maximize write throughput when appropriate, resolving the contradiction through adaptive parameter selection.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If dynamic write policy adjustment is implemented to optimize performance, then system efficiency is improved, but device complexity increases

Engineering Contradiction:
Improvesystem efficiencyVSAvoidcontrol complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The system implements feedback mechanisms that monitor performance metrics and automatically adjust write policy based on observed workload characteristics. This feedback-driven approach allows the system to optimize performance without requiring complex manual configuration or intervention, as the system self-adjusts based on real-time conditions.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The write policy adjustment system operates autonomously, monitoring its own performance and making decisions about which programming mode to use without external intervention. This self-service capability reduces the operational complexity for users while maintaining high system efficiency through automatic optimization.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS20250199724A1Dynamic Memory Address Write Policy Translation based on Performance Needs
Publication Date: 2025.06.19 MICRON TECHNOLOGY INC
  • US20250199724A1 patent drawing
  • US20250199724A1 patent drawing
  • US20250199724A1 patent drawing

AI summary

Systems and methods of memory operation involving dynamic adjustment of write policy based on performance needs. A method can include monitoring memory performance parameters related to a programming operation being scheduled, selecting a write policy based on the memory performance parameters monitored, executing a memory control process that is configured to switch between the first addressing scheme and the second addressing scheme, and programming a first superpage of the programming operation using the first addressing scheme and programing a second superpage of the programming operation using the second addressing scheme.