Dynamic Module for Decision Feedback Equalizer Timing
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Solution Overview
Problem
In high-frequency applications, the timing limitations of the speculative first-tap (tap1) in decision feedback equalizers (DFEs) pose challenges due to the complexity and speed requirements, particularly in designs exceeding 10 GHz, where the existing DFEs face difficulties in efficiently managing the timing margin and propagation delay.
Innovation Solution
A dynamic module is introduced, merging a multiplexer and a dynamic latch to reduce propagation delay and alleviate the operating margin of the speculative first-tap (tap1), utilizing a domino circuit structure with phase setting circuits and decision selection stages to manage clock signals and previous decision bits, allowing for extended timing limits by alternating operation phases between even and odd speculative paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a traditional DFE structure is used at high frequencies, then the equalization function is provided, but the propagation delay increases and timing margin is insufficient
Solution Approach 1:
The patent segments the DFE operation into two independent speculative paths (even path and odd path) that operate alternately. Each path processes different sets of taps (even taps vs. odd taps), allowing parallel processing within each clock cycle. This segmentation enables the circuit to meet timing requirements at high frequencies by dividing the computational burden across multiple specialized sub-circuits rather than one sequential path.
Solution Approach 2:
The patent implements periodic action by alternating between even and odd speculative paths in a cyclic manner controlled by clock signals. The even path operates during one clock cycle processing even-numbered taps, while the odd path operates during the next clock cycle processing odd-numbered taps. This periodic switching allows the system to maintain high-speed operation while completing all necessary equalization computations within acceptable timing margins.
2Measurement precision
If the DFE operates recursively with multiple steps, then equalization accuracy is improved, but the design complexity increases
Solution Approach 1:
The patent merges the multiplexer function and the dynamic latch function into a single integrated circuit block. The multiplexer selects between different tap values based on the speculative decision, while the dynamic latch holds the selected value for the evaluation period. By combining these two functions into one unified structure, the patent reduces the number of separate components and interconnections, thereby simplifying the overall design while maintaining the recursive equalization accuracy.
Solution Approach 2:
The speculative first-tap circuit performs self-service by using its own output to control the selection of subsequent tap values. The circuit speculatively determines the first tap value, and this speculative decision automatically controls the multiplexer selections for all subsequent taps through the decision bits. This self-controlling mechanism eliminates the need for external control logic, reducing design complexity while maintaining accurate equalization through the recursive process.
3Duration of action of moving object
If the timing limit is extended to two data unit intervals, then the operating margin is improved, but the propagation delay path becomes longer
Solution Approach 1:
The patent applies preliminary action by pre-calculating and holding tap values in dynamic latches during the precharge period before they are needed for evaluation. The multiplexers and latches prepare the correct tap values in advance based on speculative decisions, so that when the evaluation period begins, the data is already ready and positioned for immediate use. This preliminary preparation extends the effective timing window without requiring longer physical signal propagation paths.
Data Source
AI summary
A dynamic module and a decision feedback equalizer are provided. The decision feedback equalizer includes two dynamic modules, which have symmetric circuits and connections. The dynamic module includes a first domino circuit, a second domino circuit, and a storage circuit. In response to a first previous decision bit and a second previous decision bit, a first multiplexer output and a second multiplexer output are generated. The dynamic module alternatively operates in an evaluation period and a precharge period, depending on a clock signal. In the evaluation period, the first and the second multiplexer outputs are updated by the first domino circuit and the second domino circuit. In the precharge period, the first and the second multiplexer outputs are held by the storage circuit.