Dynamic MOSFET Gate Drivers for EMI Reduction
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Solution Overview
Problem
Conventional gate driver systems for power MOSFETs face challenges in minimizing electromagnetic interference (EMI) and conduction losses during switching operations, as they often rely on fixed gate resistances that fail to adjust dynamically with varying power supply conditions, leading to inefficiencies and increased EMI noise.
Innovation Solution
A dynamic MOSFET gate driver system that adjusts the gate driver turn-on and turn-off resistances within a single switching cycle to reduce EMI and conduction losses, by setting high resistance initially to slow down voltage change and then transitioning to lower resistance to minimize conduction loss and delay time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If fixed gate resistance is used in conventional gate driver systems, then the circuit structure is simple, but electromagnetic interference (EMI) and conduction losses increase during switching operations
Solution Approach 1:
The patent implements dynamic gate resistance adjustment by switching between different resistance values (Rg1, Rg2, Rg3) during the switching cycle. The gate driver transitions from a fixed resistance configuration to a dynamic resistance configuration that adapts to different switching phases, thereby reducing EMI during voltage transitions while maintaining simplicity through controlled switching of resistance elements.
Solution Approach 2:
The patent changes the gate resistance parameter dynamically during the switching operation. By adjusting the gate resistance value at different stages of the switching cycle (e.g., using higher resistance during dV/dt phases and lower resistance during conduction phases), the system reduces EMI noise while minimizing conduction losses, resolving the contradiction between fixed simplicity and harmful EMI generation.
2Ease of manufacture
If fixed gate resistance is used in conventional gate driver systems, then the device is easy to manufacture, but conduction losses increase during switching operations
Solution Approach 1:
The patent employs dynamic resistance switching that can be implemented using standard semiconductor switching devices. The gate driver dynamically selects between multiple resistance values based on the switching phase, allowing optimization of conduction losses during different operational stages while maintaining ease of manufacture through the use of conventional dynamic switching components.
Solution Approach 2:
By changing the gate resistance parameter dynamically during the switching cycle, the system optimizes conduction losses at different phases. The resistance is adjusted to match the operational requirements (e.g., higher resistance during charging phases, lower resistance during conduction phases), reducing overall energy loss while preserving manufacturability through parameter adjustment rather than structural complexity.
3Object-generated harmful factors
If high gate resistance is used initially to slow down voltage change, then EMI is reduced, but conduction loss increases
Solution Approach 1:
The patent segments the switching operation into distinct phases, each with optimized gate resistance values. By dividing the switching cycle into multiple stages (e.g., initial charging phase, transition phase, conduction phase) and assigning appropriate resistance values to each segment, the system reduces EMI during critical dV/dt phases while minimizing conduction losses during power transfer phases.
Solution Approach 2:
The patent implements periodic switching between different gate resistance values synchronized with the switching cycle. The gate driver periodically transitions between high resistance (for EMI reduction during voltage changes) and low resistance (for minimal conduction loss during steady conduction), creating a rhythmic adjustment pattern that resolves the contradiction between EMI reduction and conduction loss minimization.
Data Source
AI summary
The embodiments herein describe a dynamic metal-oxide-semiconductor field-effect transistor (MOSFET) gate driver system architecture and control scheme. The MOSFET gate driver system dynamically adjusts both the gate driver turn-on-resistance and the gate driver turn-off resistance within a single (i.e., one) switching cycle to reduce electromagnetic interference (EMI) in the system and to minimize the conduction loss of a power MOSFET during operation.