Dynamic Multi-Buffer Memory Allocation via Divider Address Control

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Solution Overview

Problem

Existing buffer management systems, particularly in data processing and network environments, face inefficiencies due to static buffer sizing, which can lead to buffer overruns or underutilization, as they fail to adapt dynamically to changing data processing rates and utilization patterns.

Innovation Solution

A hardware-implemented multi-buffer system with a dynamic buffer control circuit that adjusts the divider address between shared memory buffers based on utilization metrics, allowing for on-the-fly repartitioning of memory space to allocate more resources to heavily utilized buffers and reduce allocation to underutilized ones, thereby optimizing memory usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If static buffer sizing is used, then device complexity is reduced, but buffer overruns occur and memory utilization is inefficient

Engineering Contradiction:
Improvebuffer management complexityVSAvoidbuffer overrun prevention
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent implements dynamic buffer sizing where the buffer allocation is continuously adjusted based on real-time utilization metrics. The system monitors how much data is actually being stored in each buffer and automatically reallocates memory from underutilized buffers to overloaded ones, preventing buffer overruns while adapting to changing traffic patterns without requiring complex manual configuration.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system employs feedback mechanisms by continuously monitoring buffer utilization metrics and using this information to trigger reallocation events. When a buffer approaches capacity or becomes underutilized, the system detects this state and initiates automatic memory redistribution, creating a closed-loop control system that maintains reliable buffer operation without increasing overall system complexity.

Inventive Principle:
Principle #23Feedback

2Device complexity

If static buffer sizing is used, then device complexity is reduced, but memory utilization efficiency deteriorates

Engineering Contradiction:
Improvebuffer management complexityVSAvoidmemory utilization efficiency
Core Design Contradiction:
Device complexityVSLoss of energy

Solution Approach 1:

The patent implements dynamic buffer sizing where the buffer allocation is continuously adjusted based on real-time utilization metrics. The system monitors how much data is actually being stored in each buffer and automatically reallocates memory from underutilized buffers to overloaded ones, preventing buffer overruns while adapting to changing traffic patterns without requiring complex manual configuration.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the buffer size parameter dynamically based on utilization metrics. By monitoring actual data volumes and adjusting buffer allocations accordingly, the system ensures that memory resources are optimally utilized - neither wasted in oversized buffers nor insufficient in undersized ones - thereby improving overall memory efficiency without proportionally increasing device complexity.

Inventive Principle:
Principle #35Parameter changes

3Loss of energy

If dynamic buffer repartitioning is implemented, then memory utilization is optimized, but device complexity increases

Engineering Contradiction:
Improvememory utilization efficiencyVSAvoidbuffer control circuit complexity
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The patent implements dynamic buffer sizing where the buffer allocation is continuously adjusted based on real-time utilization metrics. The system monitors how much data is actually being stored in each buffer and automatically reallocates memory from underutilized buffers to overloaded ones, preventing buffer overruns while adapting to changing traffic patterns without requiring complex manual configuration.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The buffer management system operates autonomously by automatically monitoring its own utilization metrics and triggering reallocation events without external intervention. The control circuit detects when buffers need resizing and performs the repartitioning independently, reducing the need for complex external control mechanisms while still achieving optimized memory utilization.

Inventive Principle:
Principle #25Self-service

4Reliability

If dynamic buffer repartitioning is implemented, then buffer overrun prevention is improved, but device complexity increases

Engineering Contradiction:
Improvebuffer overrun preventionVSAvoidbuffer control circuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements dynamic buffer sizing where the buffer allocation is continuously adjusted based on real-time utilization metrics. The system monitors how much data is actually being stored in each buffer and automatically reallocates memory from underutilized buffers to overloaded ones, preventing buffer overruns while adapting to changing traffic patterns without requiring complex manual configuration.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system employs feedback mechanisms by continuously monitoring buffer utilization metrics and using this information to trigger reallocation events. When a buffer approaches capacity or becomes underutilized, the system detects this state and initiates automatic memory redistribution, creating a closed-loop control system that maintains reliable buffer operation without increasing overall system complexity.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS9026735B1Method and apparatus for automated division of a multi-buffer
Publication Date: 2015.05.05 MARVELL ISRAEL (M L S L) LTD
  • US9026735B1 patent drawing
  • US9026735B1 patent drawing
  • US9026735B1 patent drawing

AI summary

Systems and methods are provided for a hardware-implemented multi-buffer. A system includes a buffer memory comprising a shared memory space, where the memory space is shared between a first buffer and a second buffer, and where a dynamic delineation of the memory space between the first buffer and the second buffer is identified by a divider address. A dynamic buffer control circuit includes a control memory that is configured to store the divider address, a first memory utilization metric associated with the first buffer, and a second memory utilization metric associated with the second buffer. A system further includes one or more comparator circuits configured to compare the first memory utilization metric and the second memory utilization metric, where the dynamic buffer control circuit changes the divider address based on the comparison.