Dynamic Multithreading Mode Switching for Consistent Response Times
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Solution Overview
Problem
Existing computer systems face variability in response times and billing due to the transparent implementation of multithreading, which makes it difficult to determine available compute capacity and maintain high thread densities, leading to inconsistent transaction performance.
Innovation Solution
A system and method for dynamic enablement of multithreading that allows a core to be configurable between single thread and multithreading modes, enabling the execution of multiple threads on shared resources by executing an MT mode setting instruction, which determines the number of threads requested and switches between modes accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transparent multithreading is implemented in hardware, then core resource utilization increases during latency periods, but response time variability and billing variability increase due to unpredictable thread density
Solution Approach 1:
The patent implements dynamic switching between single-threaded and multithreaded modes based on workload characteristics. The OS can explicitly enable or disable MT mode and control the number of threads per core, allowing the system to adapt thread density dynamically rather than relying on unpredictable hardware behavior. This resolves the contradiction by making thread density controllable and predictable while still enabling MT when beneficial for resource utilization.
2Productivity
If high thread density is maintained to maximize MT capacity, then additional throughput capacity is achieved, but it becomes difficult to determine available compute capacity for capacity planning
Solution Approach 1:
The patent introduces explicit feedback mechanisms where the OS queries and sets the number of threads per core. This creates visibility into the actual compute capacity being provided, allowing capacity planning and billing to be based on known, controllable parameters rather than unpredictable hardware behavior. The OS can determine available capacity by querying the configured thread density and core count.
3Ease of operation
If the OS is made transparent to multithreading hardware, then no OS modification is required, but the OS cannot consistently maintain high thread densities leading to wasted MT capacity
Solution Approach 1:
The patent introduces an intermediary layer (the multithreading facility with explicit control interfaces) between the OS and the multithreading hardware. This allows the OS to maintain its existing transparency while gaining the ability to explicitly control thread density through standardized interfaces. The intermediary enables the OS to consistently maintain high thread densities without requiring fundamental OS redesign.
4Adaptability or versatility
If multithreading mode is enabled dynamically based on workload, then adaptability to different workload conditions is achieved, but hardware variability increases making capacity determination difficult
Solution Approach 1:
The patent implements explicit feedback control where the OS queries the current MT mode and thread count, then deliberately sets the desired configuration. This creates predictable, known capacity states rather than unpredictable hardware variability. The adaptability is maintained through explicit OS control decisions, but the capacity becomes deterministic and planable because the OS knows exactly what configuration is active at any time.
Data Source
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AI summary
Embodiments relate to dynamic enablement of multithreading. According to an aspect, a computer system includes a configuration with a core configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread, and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. The computer system also includes a multithreading facility configured to control the configuration to perform a method. The method includes executing in the primary thread in the ST mode, an MT mode setting instruction. A number of threads requested is obtained from a location specified by the MT mode setting instruction. Based on determining that the number of threads requested indicates multiple threads, the MT mode is enabled to execute the multiple threads including the primary thread and the one or more secondary threads.