Dynamic MUX Circuit for Slow Input Signals Without Latches
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Solution Overview
Problem
Cascode logic circuits face challenges with slow input signals, which cause delays and potential malfunctions due to the need for latches to hold static inputs during high clock periods, contributing to increased power consumption and circuit complexity.
Innovation Solution
A dynamic circuit design that includes a control circuit generating pulse signals based on selection and input signals, using NAND gates and a multiplexing logic circuit with NMOS transistors to manage signal transitions without latches, reducing signal delay and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If latches are used to hold static input signals during high clock periods in cascode logic circuits, then signal stability is maintained, but circuit complexity and power consumption increase
Solution Approach 1:
The patent removes latches from the critical signal path by extracting the signal holding function to a separate non-critical path. The slow input signal is processed through a dedicated path that does not require latching, while only the select signal path uses latches. This extraction eliminates unnecessary latches from the critical path, reducing circuit complexity while maintaining signal stability where needed.
Solution Approach 2:
The patent segments the MUX circuit into two separate paths: a critical path for the select signal that requires latching for stability, and a non-critical path for the slow input signal that does not require latching. This segmentation allows different parts of the circuit to use different designs optimized for their specific requirements, reducing overall circuit complexity while maintaining necessary signal stability.
2Stability of the object's composition
If latches are used to hold static input signals during high clock periods, then signal stability is maintained, but power consumption increases
Solution Approach 1:
The patent extracts the signal holding function from the critical path to a non-critical path, removing latches that consume power during clock high periods. By processing slow input signals through a dedicated path without latches, the circuit eliminates unnecessary power consumption while maintaining signal stability where required.
Solution Approach 2:
The patent segments the circuit to separate latched and non-latched paths, allowing power consumption to be minimized in the non-critical path while maintaining signal stability in the critical path. This segmentation enables selective power management where latches are only used where absolutely necessary.
3Adaptability or versatility
If multiple transistors are placed on the critical path between power and ground, then logic functionality is achieved, but signal delay increases
Solution Approach 1:
The patent extracts the slow input signal processing from the critical path, removing unnecessary transistors from the signal delay path. By dedicating a separate path for slow input signals that does not require latching, the critical path is streamlined with fewer transistors, reducing signal delay while maintaining full logic functionality.
Solution Approach 2:
The patent segments the signal paths to separate critical and non-critical routes. The critical path uses a streamlined design with minimal transistors for fast signal processing, while the non-critical path handles slow input signals with additional transistors that do not contribute to critical path delay. This segmentation reduces overall signal delay while preserving logic functionality.
Data Source
AI summary
A logic circuit includes a control circuit including a first logic gate to receive a selection signal and a first input signal and to output a pulse control signal and a second logic gate to receive the pulse control signal, a clock signal, and a delayed clock signal and to output a pulse signal, and a multiplexing logic circuit to receive the selection signal and the pulse signal from the control circuit, to receive at least one second, static input signal, and to output a signal corresponding to one of the first input signal and the second, static input signal based on the state of the selection signal.