Dynamic Neural Network Acceleration Unit Reconfiguration
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Solution Overview
Problem
Current circuit design methods for edge inference chips are inefficient due to high tape-out costs, computational burdens from different neural network models, and the need for additional intellectual property cores in ARM-based systems, which increase design complexity and costs.
Innovation Solution
A dynamic design method for forming neural network acceleration units that involves generating circuit description files based on model weights, selecting the appropriate files for reconfiguring chips to match specific data formats, and synthesizing core circuits for efficient data segmentation algorithms, utilizing a heterogeneous multi-core architecture with programmable logic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If ASIC architecture is used to improve computing efficiency and wiring area, then computing efficiency is improved, but tape-out cost increases and design flexibility is reduced
Solution Approach 1:
The patent employs dynamic reconfiguration capability that allows the chip architecture to change its circuit structure at runtime based on different neural network models and data formats. This dynamic approach enables the system to adapt to different computational requirements without requiring multiple fixed ASIC designs, thus maintaining high computing efficiency while improving design flexibility and reducing tape-out costs.
Solution Approach 2:
The patent creates a universal chip architecture that can handle multiple neural network models and data formats through a single design. By implementing reconfigurable circuits that can be dynamically adjusted, the system achieves multi-functionality, eliminating the need for separate ASIC designs for different applications and thereby reducing overall tape-out costs while maintaining high performance.
2Adaptability or versatility
If different neural network models are supported to reduce computational burden, then model adaptability is improved, but design complexity increases
Solution Approach 1:
The patent implements dynamic reconfiguration that allows the chip to adapt its circuit structure based on the specific neural network model being executed. This dynamic adaptation enables support for multiple models (convolutional, recurrent, transformer, etc.) and various data formats without requiring complex static design for each model, thus improving model adaptability while managing design complexity through a unified reconfigurable framework.
Solution Approach 2:
The patent utilizes parameter changes in the circuit configuration to support different neural network models. By dynamically adjusting circuit parameters such as data format handling, computational precision, and architectural topology, the system achieves high model adaptability without increasing fundamental design complexity, as all adaptations are achieved through parameter modification rather than structural redesign.
3Speed
If additional IP cores are added to ARM systems to provide high-speed bus, then communication speed is improved, but design cost and chip area increase
Solution Approach 1:
The patent integrates high-speed communication capabilities directly into the reconfigurable chip architecture, eliminating the need for separate IP cores in ARM systems. The unified architecture provides both computation and high-speed data exchange functions, achieving communication speed improvement without the additional design cost and chip area overhead of separate IP core implementations.
Data Source
AI summary
A method is disclosed to dynamically design acceleration units of neural networks. The method comprises steps of generating plural circuit description files through a neural network model; reading a model weight of the neural network model to determine a model data format of the neural network model; selecting one circuit description file from the plural circuit description files according to the model data format, so that the chip is reconfigured according to the selected circuit description file to form an acceleration unit adapted to the model data format. The acceleration unit is suitable for running a data segmentation algorithm, which may accelerate the inference process of the neural network model. Through this method the chip may be dynamically reconfigured into an efficient acceleration unit for the different model data format, thereby speeding up the inference process of the neural network model.