Dynamic NIC Switching for FPGA Power Efficiency
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Solution Overview
Problem
The power efficiency of servers equipped with FPGAs is poor due to constant power consumption regardless of processing load, leading to increased power consumption and reduced communication quality when processing loads are low or fluctuate unexpectedly.
Innovation Solution
A dual-NIC configuration with one NIC equipped with an FPGA and another normal NIC, along with a controller and switching unit that dynamically switch packet processing between the FPGA and CPU based on predetermined thresholds for power consumption and processing load.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the FPGA processes packets in low traffic periods, then packet processing capability is maintained, but power consumption increases unnecessarily
Solution Approach 1:
The patent implements dynamic switching between FPGA and CPU for packet processing based on real-time traffic load detection. The system transitions from static assignment to dynamic adaptation, adjusting the processing component according to actual needs rather than maintaining a fixed configuration.
Solution Approach 2:
The system changes the operational parameter of packet processing from fixed to variable by monitoring traffic load and switching between processing modes. When traffic exceeds a threshold, the CPU takes over; when traffic is low, the FPGA handles packets, optimizing power consumption based on actual workload conditions.
2Use of energy by moving object
If the CPU processes packets in high traffic periods, then power consumption is reduced, but communication quality deteriorates due to overload
Solution Approach 1:
The patent implements a feedback mechanism where the system continuously monitors traffic load and dynamically adjusts the processing component. When traffic exceeds the CPU's handling capacity, the system detects this condition and switches to FPGA processing, ensuring communication quality is maintained through real-time adaptive response.
Solution Approach 2:
The system transitions from static component assignment to dynamic adaptation, allowing the processing architecture to flexibly respond to changing traffic conditions. This dynamic switching ensures that the appropriate processing component is active at each moment, maintaining reliability while optimizing power usage.
3Device complexity
If a single NIC with FPGA is used, then device complexity is reduced, but adaptability to varying traffic conditions is poor
Solution Approach 1:
The patent implements a dual-NIC architecture where one NIC is equipped with FPGA and the other with CPU, creating a universal system that can handle different traffic conditions through either component. This multi-functional setup allows the system to adapt to varying requirements by selecting the appropriate processing path based on actual traffic patterns.
Data Source
AI summary
When a time period set in a timetable in which an FPGA 111 processes a packet is reached, a server switches an NIC that accepts a packet to the FPGA-equipped NIC 11. In addition, even in a time period (a time period in which a CPU processes a packet) other than the time period in which the FPGA 111 processes a packet, the server switches an NIC that accepts a packet to an FPGA-equipped NIC in a case where a power consumption amount of the server exceeds the predetermined threshold or in a case where a load of packet processing in a vGW connected to an NIC 12 exceeds a predetermined threshold.