Dynamic NOR Address Decoder Circuit for SRAM Speed and Power
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Solution Overview
Problem
Existing SRAMs face challenges in simplifying circuit construction, improving processing speed, and reducing power consumption, particularly due to increased transistor size and power consumption when increasing drive power for faster address decoding, and complexity from dynamic NOR circuits that maintain all word lines active except during decoding.
Innovation Solution
An address decoder is implemented using a combination of dynamic NOR circuits and an inverting AND circuit, which inverts and performs logical AND operations between decode units to selectively activate memory cells, eliminating the need for additional enable clock circuits and simplifying timing adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If drive power is increased to improve address decoding speed, then processing speed is improved, but transistor size and power consumption are increased
Solution Approach 1:
The patent applies dynamic circuit techniques by using dynamic NOR circuits for address decoding. The circuit uses precharging followed by conditional discharging based on address signals, enabling faster decoding without requiring proportionally larger transistors. This dynamic operation allows the circuit to achieve high speed while maintaining reasonable power consumption by only drawing significant power during the brief decoding window rather than continuously.
Solution Approach 2:
The patent employs periodic precharging of word lines followed by selective discharging during decode operations. This periodic action pattern allows the circuit to reset to a known state and then perform rapid decoding only when needed, improving overall speed while reducing average power consumption compared to continuously active circuits.
2Speed
If dynamic NOR circuits are used to improve decoding speed, then processing speed is improved, but circuit complexity increases due to all word lines being active except during decoding
Solution Approach 1:
The patent combines multiple functions into the dynamic NOR circuit structure. The same circuit that performs address decoding also serves as the word line driver, eliminating the need for separate enable clock circuits and timing adjustment mechanisms. This merging of functions simplifies the overall circuit construction while maintaining high decoding speed.
Solution Approach 2:
The dynamic NOR circuit automatically manages its own timing and control signals through the inherent behavior of dynamic logic. The precharge and decode phases are self-regulated by the circuit's internal timing, eliminating the need for external control logic and reducing overall circuit complexity.
3Use of energy by moving object
If additional enable clock circuits are added to control word line activation, then power consumption is reduced, but device complexity and timing adjustment difficulty increase
Solution Approach 1:
The patent extracts the enable clock function from being a separate external circuit and integrates it directly into the dynamic NOR circuit structure. The decoding operation itself generates the necessary timing control, removing the need for additional dedicated enable clock circuits and their associated complexity.
Solution Approach 2:
The dynamic NOR circuit is designed to perform multiple functions: address decoding, word line selection, and timing control. This multi-functionality eliminates the need for separate enable clock circuits, reducing overall device complexity while maintaining effective power management through selective word line activation.
Data Source
AI summary
The address decoder includes: a plurality of decode units each formed by a combinational logic circuit; an inverting circuit which inverts an output of said decode unit; an AND circuit which performs a logical AND operation between an output signal of said decode unit, which has been inverted by said inverting circuit, and another one of said plurality of decode units. This arrangement makes it possible to simplify the circuit construction, to improve the processing speed, and to reduce power consumption.