Dynamic ODT Matching for Non-Volatile Memory Signal Integrity
Solution Overview
Problem
The increasing number of storage dies and higher transfer speeds in non-volatile memory systems lead to impedance mismatches at the interface between the storage medium package and the storage controller, causing energy reflections and degrading signal integrity and performance.
Innovation Solution
A dynamic on-die-termination (ODT) scheme is implemented with multiple ODT stages, each having different resistances, which initially sets a low ODT resistance and gradually phases it out over time, eventually disabling ODT when impedance mismatches are no longer present, using a plurality of resistor pairs and switch-controlled ODT circuitry to manage resistance levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple memory dies are stacked and transfer frequencies are increased to increase capacity and operating speed, then storage capacity and performance are improved, but impedance mismatch at the interface causes energy reflections and degrades signal integrity
Solution Approach 1:
The patent implements dynamic ODT adjustment that changes termination resistance values based on the stage of the read operation. During early clock cycles when impedance mismatch is most severe, lower ODT values (e.g., 50-70 ohms) are applied to absorb reflections. As the operation progresses and signal stability improves, ODT values are increased or disabled, optimizing power consumption while maintaining signal integrity.
Solution Approach 2:
The patent changes the termination resistance parameter dynamically during read operations. Multiple ODT stages with different resistance values (e.g., 50 ohms, 70 ohms, 90 ohms, or disabled) are sequentially applied based on the read operation progress, allowing the system to adapt to changing signal conditions and optimize both signal integrity and power consumption.
2Reliability
If ODT is continuously enabled to maintain signal integrity, then reflections are absorbed, but power consumption increases
Solution Approach 1:
The patent applies ODT in periodic stages during read operations rather than continuously. The ODT control circuit enables different ODT values for specific numbers of clock cycles (e.g., first ODT value for first N clock cycles, second ODT value for next M clock cycles), then disables ODT for the remainder of the operation. This periodic application maintains signal integrity when needed while reducing power consumption when reflections are no longer an issue.
Solution Approach 2:
The patent dynamically adjusts ODT settings based on the operational stage rather than maintaining a static configuration. The system transitions from low ODT values during early clock cycles to higher ODT values or disabled states during later cycles, optimizing the balance between signal integrity and power consumption throughout the read operation.
3Speed
If high transfer speeds are used to improve performance, then data transfer efficiency increases, but impedance mismatch effects are amplified causing signal degradation
Solution Approach 1:
The patent applies preliminary termination with lower ODT values at the beginning of read operations to counteract the anticipated impedance mismatch effects that occur at high transfer speeds. By pre-applying appropriate termination during the critical early clock cycles where reflections are most problematic, the system maintains signal integrity even at high data transfer rates.
Solution Approach 2:
The patent implements dynamic ODT adjustment that adapts to the high-speed operation conditions. The system uses lower ODT values during early clock cycles to combat reflections caused by high-speed signal transitions, then transitions to higher ODT values or disabled states as the operation progresses, maintaining signal integrity throughout the high-speed data transfer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively absorbs energy reflections without negatively impacting power consumption or performance, ensuring reliable data transfer across high-capacity and high-frequency storage systems.
Implementation Method 1
a plurality of resistor pairs, wherein each resistor pair of the plurality of resistor pairs includes (i) a pull-up resistor selectively coupled to the signal path via a first switch, and (ii) a pull-down resistor selectively coupled to the signal path via a second switch
Data Source
AI summary
A data storage system includes a plurality of memory dies and interface circuitry, including a receiver configured to receive pulses of a read clock signal; an I/O contact pad coupled to the receiver via a signal path of an interface channel; and on-die-termination (ODT) circuitry coupled to the I/O contact pad and the receiver. The ODT circuitry includes a plurality of resistor pairs, each including a pull-up resistor selectively coupled to the signal path via a first switch, and a pull-down resistor selectively coupled to the signal path via a second switch; and ODT control circuitry configured to enable ODT at the interface circuitry by causing each of the switches to be closed during a first stage of the read operation, and disable ODT at the interface circuitry by causing each of the switches to be open during a final stage of the read operation.