Dynamic On-Die Termination Control for Low-Power Memory Buses

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Solution Overview

Problem

Contemporary memory systems face signal distortion issues due to impedance mismatches on signal buses, which are alleviated by termination elements but result in increased current consumption.

Innovation Solution

An on-die termination (ODT) circuit that includes an ODT control circuit and an ODT section, activated/deactivated based on read and write latency control signals, to compensate for impedance mismatches on data and command/address buses, thereby reducing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If termination elements are provided on signal lines to compensate for impedance mismatches, then signal distortion is reduced, but current consumption increases

Engineering Contradiction:

Improvesignal qualityVSAvoidcurrent consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent implements dynamic termination by controlling the ODT section to be activated or deactivated based on operational modes. The ODT control circuit generates control signals that dynamically adjust the termination state, allowing the system to optimize between signal quality and power consumption by enabling termination only when necessary (e.g., during specific read/write operations) rather than maintaining it continuously

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the electrical state parameter of the termination resistor by controlling its activation and deactivation. The ODT control circuit modifies the resistance parameter dynamically by switching the ODT section on or off based on operational requirements, thereby adjusting the electrical characteristics of the signal line to match impedance only when needed, reducing power consumption during periods when termination is not required

Inventive Principle:

Principle #35Parameter changes

2Reliability

If termination resistors are continuously activated to maintain impedance matching, then signal reflections are minimized, but power consumption increases

Engineering Contradiction:

Improvesignal integrityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

The patent implements periodic activation of the ODT section based on operational modes. The ODT control circuit periodically enables or disables the termination resistor according to the timing of read/write operations and latency requirements, rather than maintaining continuous termination. This periodic action ensures signal integrity during critical operations while minimizing power consumption during idle or non-critical periods

Inventive Principle:

Principle #19Periodic action

Data Source

PatentUS8928349B2On-die termination circuit, semiconductor memory device and memory system

Publication Date: 2015.01.06 SAMSUNG ELECTRONICS CO LTD

AI summary

An ODT circuit is activated/deactivated in response to a latency control signal or a clock enable signal. The ODT circuit includes an ODT control circuit and an ODT section. The ODT control circuit determines an ODT status based on a read latency control signal (RL) and/or a write latency control signal (WL) to generate an ODT control signal. The ODT section is activated/deactivated in response to the ODT control signal.