Dynamic On-Die Termination for High-Speed Memory Signal Margins
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Solution Overview
Problem
High-speed signaling systems with single on-die termination schemes experience sub-optimal performance due to impedance discontinuity and signal attenuation, leading to reduced signaling margins and increased error rates.
Innovation Solution
Implementing multiple, graduated on-die termination structures per high-speed signaling line, allowing for switchable selection between high-load and low-load termination loads based on whether the memory module is the destination for incoming signals, thereby optimizing impedance matching and energy absorption without attenuating incoming signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If single on-die termination structure is used, then device complexity is reduced, but signaling margins deteriorate due to impedance discontinuity and signal attenuation
Solution Approach 1:
The termination structure is segmented into multiple distinct termination structures (first termination structure and second termination structure) with different load characteristics. This segmentation allows each structure to serve a specific function: one for impedance matching and another for energy absorption, thereby improving signaling margins without excessive complexity increase.
Solution Approach 2:
Different termination structures are applied at different locations or conditions along the signal path. The first termination structure provides high-load termination for impedance matching at specific points, while the second provides low-load termination for energy absorption at other points, optimizing local signal characteristics to improve overall reliability.
2Manufacturing precision
If high-load termination is applied, then impedance matching is improved, but signal attenuation increases leading to reduced signaling margins
Solution Approach 1:
High-load termination is applied locally at specific termination structures where impedance matching is critical, rather than uniformly across all termination points. This localized application maintains impedance matching where needed while avoiding excessive attenuation elsewhere.
Solution Approach 2:
The termination function is segmented between different structures: the first termination structure handles impedance matching with high-load termination, while the second termination structure handles energy absorption with low-load termination, preventing signal attenuation from compromising signaling margins.
3Reliability
If multiple graduated on-die termination structures are implemented, then signaling margins are enhanced, but device complexity increases
Solution Approach 1:
The termination system is segmented into a small number of distinct termination structures (first and second termination structures) rather than continuously variable terminations. This segmentation provides the benefits of multiple termination options while limiting complexity to a manageable number of discrete structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances signaling margins, reduces bit error rates, and provides additional headroom for increased signaling rates by effectively managing impedance and reflections.
Implementation Method 1
allowing for switchable selection between high-load and low-load termination loads based on whether the memory module is the destination for incoming signals, thereby optimizing impedance matching and energy absorption without attenuating incoming signals
Data Source
AI summary
In an integrated circuit device having dynamically selected on-die termination, a set of data inputs are coupled respectively to a set of termination circuits, each termination circuit having multiple controllable termination impedance configurations. A termination control signal input is provided to receive an indication that the integrated circuit device is to apply one of the controllable termination impedance configurations at each of the data inputs, and a logic circuit applies one of a first and a second of the controllable termination impedance configurations at the data inputs based on the indication received at the termination control signal input and an internal state of the memory device, such that during a first internal state corresponding to the reception of write data on the data inputs, the first of the controllable termination impedance configurations is applied at each of the data inputs, and during a second internal state following the first internal state, the second of the controllable termination impedance configurations is applied at each of the data inputs.


