Time-Interleaved Dynamic Op-Amp Circuit for Stable Input Capacitance
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Solution Overview
Problem
Existing ultrahigh-speed ADC circuits face challenges in stabilizing parasitic capacitance on input wiring, leading to reduced spurious free dynamic range (SFDR) due to nonlinear capacitance and charge coupling effects in dynamic operational amplifiers.
Innovation Solution
A high-speed high-linearity time-interleaved dynamic operational amplifier circuit is designed with specific MOS transistor configurations and connections to stabilize parasitic capacitance, including PMOS and NMOS transistors in series, and a capacitor to counteract switch charge coupling, ensuring stable capacitance values during sampling and amplification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a dynamic operational amplifier circuit is used to drive heavy current in ultrahigh-speed ADC, then the driving capability is improved, but nonlinear capacitance and charge coupling effects increase, deteriorating the SFDR
Solution Approach 1:
The patent introduces a compensation capacitor Cc as an intermediary element between the input sampling node and ground. This capacitor mediates the charge coupling effects by providing a dedicated path for charge redistribution, thereby isolating the sampling node from harmful charge injection while maintaining the heavy current driving capability of the dynamic operational amplifier.
Solution Approach 2:
The patent optimizes the value of the compensation capacitor Cc to specifically counteract the nonlinear capacitance effects. By carefully selecting Cc such that Cc >= Cs/2 (where Cs is the sampling capacitor), the circuit parameters are adjusted to minimize charge coupling and stabilize the total capacitance at the sampling node, improving SFDR while maintaining driving capability.
2Speed
If switch structures are used for sampling and holding, then the sampling speed is improved, but clock charge couples to the sampling capacitor, deteriorating the sampling signal
Solution Approach 1:
The patent extracts the charge coupling problem by introducing a separate compensation capacitor Cc that is specifically dedicated to handling clock charge injection. This allows the main sampling capacitor Cs to focus on signal storage while Cc absorbs and compensates for the harmful clock charge, thereby maintaining high sampling speed without signal deterioration.
Solution Approach 2:
The compensation capacitor Cc is pre-configured with appropriate capacitance value to anticipate and counteract the clock charge coupling effects before they deteriorate the sampling signal. By having Cc in place with Cc >= Cs/2, the circuit proactively neutralizes the harmful effects of switch charging, preserving signal integrity during high-speed sampling operations.
3Reliability
If two stages of amplification and reset are implemented, then the signal conditioning is improved, but the parasitic capacitance of input transistors varies greatly, affecting stability and SFDR
Solution Approach 1:
The patent applies preliminary action by pre-charging the compensation capacitor Cc to the common-mode voltage level before the actual sampling and amplification processes. This preliminary voltage establishment ensures that when the dynamic operational amplifier switches between amplification and reset states, the parasitic capacitance variations are compensated, maintaining stable total capacitance and improving SFDR.
Solution Approach 2:
The compensation capacitor Cc creates a feedback mechanism that automatically compensates for parasitic capacitance variations in the input transistors. As the parasitic capacitance changes during amplification and reset cycles, the voltage across Cc adjusts accordingly to maintain stable total capacitance at the sampling node, thereby preserving signal conditioning quality and SFDR performance.
Data Source
AI summary
A high-speed high-linearity time-interleaved dynamic operational amplifier circuit includes a first current channel and a second current channel. The first current channel includes a first MOS transistor, a second MOS transistor and a third MOS transistor which are sequentially connected in series between a high level and a ground level. The first MOS transistor and the second MOS transistor have opposite conductivity types. A control end of the first MOS transistor is connected to a control end of the second MOS transistor. The second current channel includes a fourth MOS transistor, a fifth MOS transistor and a sixth MOS transistor which are sequentially connected in series between the high level and the ground level. The fourth MOS transistor and the fifth MOS transistor have opposite conductivity types. A control end of the fourth MOS transistor is connected to a control end of the fifth MOS transistor.