Dynamic Packet Buffer Bypass Using Preemptable Write Queues

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Solution Overview

Problem

Network devices face inefficiencies in packet buffering due to the load on memory bus connections from writing and reading packets, which can lead to increased latency and resource utilization, particularly when buffer queues are full.

Innovation Solution

Implementing a traffic manager with preemptable and non-preemptable write queues, where packets are selectively routed based on buffer queue lengths, allowing for dynamic memory bypass by prioritizing non-preemptable queues when full and preempting packets from preemptable queues before they are written to memory.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If packets are written to memory device, then packet buffering capacity is improved, but memory bus load increases causing latency

Engineering Contradiction:
Improvepacket buffering capacityVSAvoidtransmission latency
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The write queues are segmented into preemptable and non-preemptable portions, allowing selective handling of packets based on their retrieval probability. This segmentation enables the system to avoid writing packets to memory that are likely to be retrieved anyway, thus reducing memory bus load and latency while maintaining buffering capacity for packets that need persistent storage.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system performs preliminary actions by checking whether packets in preemptable queues are candidates for retrieval before committing them to memory. This preliminary check allows the system to intercept and retrieve packets from the queue manager before they are written to memory, avoiding unnecessary memory bus transactions and reducing latency.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If dynamic bypass is implemented, then memory bus bandwidth is saved, but queue management complexity increases

Engineering Contradiction:
Improvememory bus bandwidth utilizationVSAvoidqueue management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

Write queues are divided into preemptable and non-preemptable segments, with clear distinction in their handling. The preemptable portion allows for dynamic bypass opportunities, while the non-preemptable portion ensures packets are written to memory. This segmentation provides a structured approach to managing complexity while enabling bandwidth optimization.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system performs preliminary identification of packets that are candidates for retrieval before they are committed to memory. By checking the preemptable queue status in advance, the system can make informed decisions about whether to proceed with memory writes, thus optimizing bandwidth usage without requiring complex runtime interventions.

Inventive Principle:
Principle #10Preliminary action

3Loss of time

If packets are retrieved from traffic manager before memory write, then latency is reduced, but risk of data loss increases

Engineering Contradiction:
Improvepacket retrieval latencyVSAvoidpacket data integrity
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

The write queues are segmented into preemptable and non-preemptable portions, with the preemptable portion being the only candidate for early retrieval. This segmentation ensures that only packets explicitly marked as preemptable are at risk of early retrieval, while non-preemptable packets are safely written to memory, thus maintaining data integrity while enabling latency reduction where appropriate.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system dynamically determines whether packets in preemptable queues are candidates for retrieval based on current system state and buffer queue lengths. This dynamic assessment allows the system to adaptively decide on early retrieval, balancing latency reduction with data integrity by only preempting packets when it is safe and beneficial to do so.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS9922000B2Packet buffer with dynamic bypass
Publication Date: 2018.03.20 MARVELL ISRAEL (M L S L) LTD
  • US9922000B2 patent drawing
  • US9922000B2 patent drawing
  • US9922000B2 patent drawing

AI summary

A write queue, for queuing a packet in a traffic manager coupled to a memory device, is selected from among a preemptable write queue configured to queue packets that are candidates for being retrieved from the traffic manager before the packets are written to the memory device and a non-preemptable write queue configured to queue packets that are not candidates for being retrieved from the traffic manager before the packets are written to the memory device. The packet is written to the selected write queue. A read request is generated for retrieving the packet from the memory device, and it is determined whether the packet is queued in the preemptable write queue. If the packet is queued in the preemptable write queue, the packet is extracted from the preemptable write queue for retrieving the packet from the traffic manager before the packet is written to the memory device.