Dynamic Packet Reordering System for Wireless Networks
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Solution Overview
Problem
Conventional data network systems face processing latencies and increased costs due to the need for intermediate memories when reversing encoding processes in real-time and non-real-time service delivery, particularly in wireless communication networks.
Innovation Solution
A dynamic packet reordering system that operates on-the-fly using parallel processing to de-interleave, calculate LLR metrics, and map modulation symbols into decodable packets, thereby reducing or eliminating the need for intermediate memories and minimizing processing latencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional step-by-step processing is used to reverse encoding processes, then data can be decoded accurately, but processing latency increases and intermediate memories are required
Solution Approach 1:
The patent pre-calculates and stores reordering tables during system initialization or idle periods, so that when data processing is needed, the system can directly use these pre-computed tables to reorder packets without performing complex calculations in real-time. This preliminary action eliminates the need for intermediate memories during active processing and reduces latency while maintaining decoding accuracy.
Solution Approach 2:
The patent replaces the conventional mechanical step-by-step processing approach with a parallel processing architecture that uses pre-computed reordering tables. Instead of sequentially processing each encoding step with intermediate memory storage, the system uses parallel table lookups and direct packet reordering, substituting the mechanical sequential process with a more efficient parallel approach that reduces latency.
2Ease of operation
If intermediate memories are used in conventional processing, then data can be processed step by step, but device complexity and cost increase
Solution Approach 1:
The patent extracts the reordering functionality from the main processing path and implements it through pre-computed tables that are applied directly to packets. This extraction eliminates the need for intermediate memories and complex reordering logic during active data processing, reducing device complexity while maintaining the ability to process data systematically.
Solution Approach 2:
By pre-computing reordering tables during initialization or idle periods, the patent removes the need for complex real-time reordering logic and intermediate memories. The system simply looks up pre-computed table entries during packet processing, significantly reducing device complexity and cost while preserving systematic processing capability.
3Productivity
If intermediate memories are used for encoding reversal, then processing can be done sequentially, but memory requirements increase
Solution Approach 1:
The patent pre-computes reordering tables during idle periods or initialization, so that during active packet processing, no intermediate memories are needed. The system uses these pre-computed tables to directly reorder packets in parallel, eliminating the need for large intermediate memory structures while maintaining sequential processing capability through the table lookup mechanism.
Solution Approach 2:
Instead of using large intermediate memories to store data during sequential processing, the patent creates a copy of the reordering information in the form of pre-computed tables. These tables are much smaller than intermediate memories would need to be, and they enable parallel processing without requiring significant memory resources during active data handling.
Data Source
AI summary
Methods and apparatus for dynamic packet reordering. In an aspect, a method is provided for processing slot data on-the-fly to produce decodable packets, wherein the slot data includes interleaved modulation symbols. The method includes de-interleaving a stream of the interleaved modulation symbols to produce a stream of modulation symbols, calculating parallel streams of LLR metrics based on the stream of modulation symbols, and mapping the parallel streams of LLR metrics to produce a stream of decodable packets. In another aspect, an apparatus is provided the includes de-interleaving logic to de-interleave a stream of interleaved modulation symbols to produce a stream of modulation symbols, metric processing logic configured to produce parallel streams of LLR metrics based on the stream of modulation symbols, and mapping logic configured to map the parallel streams of LLR metrics to produce a stream of decodable packets.