Dynamic Logical Page Write Ordering for Flash Memory
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Solution Overview
Problem
In data storage devices, the suspension of programming one memory die to program another can lead to delays in programming operations, particularly due to the need to manage parity writes and other data writes efficiently.
Innovation Solution
A data storage device with a controller that determines the availability of each memory die and dynamically changes the programming order based on die availability, optimizing the order of logical page writes to minimize delays and improve performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If programming operations are performed in a fixed order across multiple memory dies, then the programming process is simple to manage, but delays occur when certain dies need to be suspended for parity writes or other operations
Solution Approach 1:
The patent implements dynamic programming order adjustment by monitoring the availability status of each memory die and changing the programming sequence in real-time. When a die becomes unavailable for programming (e.g., undergoing erase, read, or parity write operations), the controller dynamically reorders the programming queue to skip unavailable dies and program only available ones, thereby maintaining high productivity without fixed-order constraints.
Solution Approach 2:
The system changes the programming parameter of 'programming order' based on the availability status of memory dies. By tracking each die's state (available, erasing, reading, parity write) and adjusting the programming sequence accordingly, the system optimizes throughput while avoiding delays caused by suspended programming operations.
2Productivity
If the programming order is changed dynamically based on die availability, then programming delays are reduced and throughput improves, but the complexity of managing programming operations increases
Solution Approach 1:
The controller implements a feedback mechanism by continuously monitoring the availability status of each memory die and using this information to adjust the programming order. The system receives feedback about die states (erasing, reading, parity write operations) and dynamically reorders programming operations accordingly, optimizing metapage write completion while managing complexity through systematic status tracking.
Solution Approach 2:
The programming management system serves itself by automatically detecting die availability and reordering operations without external intervention. The controller autonomously manages the programming queue, selecting which dies to program next based on their current state, thereby reducing the need for complex external scheduling while improving throughput.
3Reliability
If memory dies are suspended for parity writes, then data integrity is maintained, but the completion time of metapage writes increases
Solution Approach 1:
The system performs preliminary actions by identifying and suspending only the specific dies that need to undergo parity writes, while continuing to program other available dies without suspension. This selective approach maintains data integrity for dies requiring parity operations while minimizing the impact on overall metapage write completion time by keeping other dies productive.
Solution Approach 2:
The patent segments the programming operations by die, allowing independent management of each die's programming status. By dividing the metapage write operation into individual die-level tasks, the system can suspend only the necessary dies for parity writes while continuing programming on other dies, thereby maintaining data integrity without extending the overall metapage write duration.
Data Source
AI summary
In some situations, the programming of one memory die can be suspended in favor of the programming of another memory die. This can lead to a delay in certain programming operations. To avoid this problem, a data storage device can perform dynamic logical page write ordering by determining an availability of each memory die of a plurality of memory dies and changing a programing order of the plurality of memory dies in response to the determined availability.