Dynamic Parity Placement in Memory Storage Devices

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Solution Overview

Problem

Traditional data storing methods for rewritable non-volatile memory result in waste of storage space and limited error correction capability due to fixed parity placement, which cannot effectively handle excessive error bits.

Innovation Solution

A data storing method where parity is generated and programmed into a physical programming unit after the data unit, with a mark indicating its location, allowing rapid identification and correction of errors without fixed parity positions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If parity is placed at fixed positions in the memory storage system, then error correction capability is maintained, but storage space is wasted when data requires parity across multiple memory dies

Engineering Contradiction:
Improveerror correction capabilityVSAvoidstorage space waste
Core Design Contradiction:
ReliabilityVSLoss of substance

Solution Approach 1:

The patent applies dynamics by making the parity placement flexible rather than fixed. The parity is dynamically positioned in the first available physical programming unit after the data is written, rather than being statically placed at predetermined locations. This dynamic placement allows efficient use of storage space across multiple memory dies while maintaining error correction capability.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent segments the memory storage system into multiple physical programming units with distinct functions. Each physical programming unit can independently store data or parity, and the system manages these segmented units to optimize both error correction and storage efficiency. The segmentation allows flexible allocation of parity across different memory dies based on actual data storage requirements.

Inventive Principle:
Principle #1Segmentation

2Reliability

If dummy data is filled into physical programming units to generate parity across multiple memory dies, then parity can be stored, but storage space is wasted

Engineering Contradiction:
Improveparity storage capabilityVSAvoidstorage space waste
Core Design Contradiction:
ReliabilityVSLoss of substance

Solution Approach 1:

The patent extracts the unnecessary dummy data filling step from the traditional parity generation process. Instead of filling dummy data into all required physical programming units, the system only writes actual parity data into the first available physical programming unit after the data, eliminating the waste of storage space while maintaining parity storage capability.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent discards the practice of filling dummy data into physical programming units. By removing this unnecessary step and only writing actual parity data where needed, the system recovers wasted storage space while still maintaining the ability to store and retrieve parity for error correction.

Inventive Principle:
Principle #34Discarding and recovering

3Reliability

If traditional fixed parity placement is used, then error correction can be performed, but the system cannot efficiently handle excessive error bits

Engineering Contradiction:
Improveerror correction functionVSAvoidhandling excessive error bits
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The dynamic parity placement mechanism enhances the system's adaptability to handle excessive error bits. When errors are detected, the system can dynamically locate the parity in the first available physical programming unit after the data, providing flexible access to correction information regardless of the data's position or the extent of errors present.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS9436547B2Data storing method, memory control circuit unit and memory storage device
Publication Date: 2016.09.06 PHISON ELECTRONICS
  • US9436547B2 patent drawing
  • US9436547B2 patent drawing
  • US9436547B2 patent drawing

AI summary

A data storing method, a memory control circuit unit and a memory storage device are provided. The method includes: generating a parity according to first data. The method also includes: when programming the first data into first physical programming unit, programming at least one mark into redundancy bit area of the first physical programming unit. The method further includes: programming the parity into at least one second physical programming unit arranged after the first physical programming unit, and the at least one mark indicates that the parity is programmed into the at least one second physical programming unit.