Dynamic PCIe Lane Access Switching via Flexible I/O Adapter

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Solution Overview

Problem

In computing systems, existing PCIe interconnect architectures require a reboot cycle to change communication links, limiting flexibility and efficiency in dynamic lane assignment between different root spaces, which hinders performance and power management.

Innovation Solution

A flexible I/O adapter (FIA) dynamically assigns access to physical layer lanes between PCIe controllers without a reboot cycle, enabled by a power management controller (PMC) that reconfigures lane access based on power state transitions and traffic conditions, allowing seamless switching between root spaces.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If PCIe lanes are statically assigned to root spaces, then system stability is maintained, but flexibility and adaptability in lane assignment deteriorate

Engineering Contradiction:
Improvelane assignment flexibilityVSAvoidlane reconfiguration complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements dynamic lane assignment by introducing a lane assignment controller that can reconfigure which root space (host CPU or ME processor) has access to PCIe lanes at runtime. This allows the system to transition from static to dynamic lane assignment, enabling adaptability while managing complexity through centralized control logic that handles reconfiguration based on power states and traffic conditions.

Inventive Principle:
Principle #15Dynamics

2Productivity

If a reboot cycle is required to change communication links, then system reliability is improved, but productivity and response time deteriorate

Engineering Contradiction:
Improvelane reassignment speedVSAvoidlink stability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary action by detecting power state transitions and traffic conditions in advance, then proactively reassigning PCIe lanes before communication needs change. The lane assignment controller monitors system state and performs reconfiguration proactively, avoiding the need for reactive reboot cycles and maintaining link stability through controlled transitions.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system transitions from static lane assignment requiring reboots to dynamic lane assignment that adapts in real-time. The lane assignment controller enables runtime reconfiguration based on power states and traffic conditions, improving productivity by eliminating reboot cycles while maintaining reliability through controlled, monitored transitions.

Inventive Principle:
Principle #15Dynamics

3Adaptability or versatility

If PCIe links are established statically, then device complexity is reduced, but adaptability to different power states and traffic conditions deteriorates

Engineering Contradiction:
Improvepower state adaptabilityVSAvoiddynamic reconfiguration complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements feedback mechanisms where the lane assignment controller continuously monitors power state transitions and PCIe traffic conditions. Based on this feedback, the controller dynamically adjusts lane assignments to optimize system performance and power consumption, enabling adaptability to different operating conditions while managing complexity through centralized control logic.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS10817454B2Dynamic lane access switching between PCIe root spaces
Publication Date: 2020.10.27 INTEL CORP
  • US10817454B2 patent drawing
  • US10817454B2 patent drawing
  • US10817454B2 patent drawing

AI summary

An apparatus includes physical layer circuitry with lanes to couple the apparatus to endpoint devices. a first input/output (I/O) controller to couple a first processor to the physical layer circuitry, and a second I/O controller to couple a second processor to the physical layer circuitry. The first and second I/O controllers are compatible with a Peripheral Component Interconnect Express (PCIe)-based protocol. The apparatus also includes a flexible input/output adapter (FIA) coupling the first and second I/O controllers to the lanes. The FIA selectively assigns access to each lane of the lanes by either the first or second I/O controller. The apparatus also includes a power management controller (PMC) communicably coupled to the FIA. The PMC causes the FIA to dynamically assign access to at least one of the lanes by the first or second I/O controller without a reboot cycle.