Dynamic PCIe Port Assignment for Bandwidth Aggregation
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Solution Overview
Problem
Existing high-speed data interfaces, such as PCIe, face challenges in efficiently utilizing bandwidth due to complexity and cost associated with wider lanes, leading to limitations in supporting complex functions and increased risk of data corruption.
Innovation Solution
The use of multiple smaller PCIe ports to masquerade as a single connection, allowing a single function to utilize combined bandwidth while maintaining discrete device visibility to the host system, through dynamic and updatable mapping between functions and ports, reducing traffic and complexity in NUMA systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wider PCIe lanes are used to accommodate complex functions, then bandwidth is improved, but device complexity and cost increase
Solution Approach 1:
The patent divides a wide PCIe interface (e.g., x16) into multiple smaller independent interfaces (e.g., four x4 lanes). Each lane can be independently configured and assigned to different functions, allowing complex functions to utilize multiple lanes for aggregated bandwidth while keeping each individual lane simple and cost-effective.
Solution Approach 2:
Multiple smaller PCIe lanes are designed to be universally assignable to different functions through dynamic configuration. The same set of physical lanes can be allocated to support various function combinations based on system requirements, making the interface flexible and multi-functional without requiring dedicated wide lanes for each specific function.
2Productivity
If larger interfaces with higher bandwidth are employed, then complex functions are supported, but cost increases
Solution Approach 1:
Instead of implementing a single wide PCIe interface that requires more expensive physical layers and signaling, the system segments the bandwidth requirement across multiple smaller, less expensive lanes. Each lane uses simpler, more cost-effective physical implementation while collectively providing the required aggregate bandwidth through parallel operation.
3Productivity
If multiple smaller PCIe ports are used, then bandwidth utilization is improved, but device configuration complexity increases
Solution Approach 1:
The patent implements dynamic lane assignment where the configuration of multiple smaller PCIe lanes can be changed at runtime based on system needs. The host system can dynamically allocate and re-allocate lanes to different functions without requiring physical reconfiguration, making the configuration process flexible and adaptable to changing requirements.
4Adaptability or versatility
If wider interfaces are used to support complex functions, then function capability is improved, but reliability decreases due to increased data corruption risk
Solution Approach 1:
By segmenting a wide interface into multiple smaller independent lanes, the patent reduces the complexity and error potential of each individual transmission path. Each smaller lane has simpler signaling and lower susceptibility to data corruption, while the aggregation of multiple reliable lanes provides the necessary function capability with improved overall reliability through redundancy and independent error handling.
Data Source
AI summary
An electronics adapter and method are disclosed herein. The electronics adapter can include a plurality of interface ports, with each interface port from the device coupled to a processor from a plurality of processors, and a controller communicatively coupled to the interface ports. The controller may be configured to determine a function or transaction attributes, which are serviced by instructions executed by one of the processors. The controller may be further configured to determine at least one interface port on the adapter to transmit the transaction based on the function or the attributes using an updatable mapping between the function or the attributes and the interface port, and transmit a request for the transaction using the interface port for processing of the transaction by the processor coupled to the interface port.