Dynamic Performance Switching Processor Architecture
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Solution Overview
Problem
Existing processor architectures face challenges in balancing high-performance and low-power consumption, leading to inefficiencies and increased hardware costs due to the need for heterogeneous computing architectures with multiple types of processor cores.
Innovation Solution
A processor architecture that includes an execution unit coupled with a performance switching module, which dynamically adjusts clock rate, voltage, and instruction execution cycle based on performance requirements, allowing the processor to switch between high-performance and low-power modes without the need for multiple execution units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a processor uses high-processing frequency and multi-stage pipeline architecture to achieve high performance, then processing speed is improved, but power consumption increases
Solution Approach 1:
The processor dynamically adjusts its operating parameters including processing frequency, pipeline depth, and voltage levels based on the complexity and requirements of the current task. This allows the processor to operate at high performance when needed while reducing power consumption during simpler operations, resolving the contradiction between speed and energy usage.
Solution Approach 2:
The system changes multiple operating parameters simultaneously (frequency, voltage, pipeline configuration) to achieve different performance states. By adjusting these parameters dynamically, the processor can transition between high-performance and low-power modes to match task requirements, addressing the speed-power consumption tradeoff.
2Use of energy by moving object
If a processor uses low-processing frequency and simplified pipeline architecture to achieve low power consumption, then power efficiency is improved, but processing speed decreases
Solution Approach 1:
The processor dynamically adapts its architecture and operating parameters based on task requirements. When complex tasks are detected, the system increases processing frequency and activates additional pipeline stages. When simple tasks are detected, it reduces frequency and uses a simplified pipeline, ensuring high power efficiency without permanently sacrificing performance capability.
Solution Approach 2:
A single processor unit is designed to perform multiple functions across different performance levels by dynamically reconfiguring its pipeline architecture and operating parameters. This universal design eliminates the need for separate high-performance and low-power processors, allowing one unit to adapt to various computational demands while optimizing the power-performance balance.
3Adaptability or versatility
If heterogeneous computing architecture with multiple processor core types is used to achieve both high performance and low power consumption, then application versatility is improved, but hardware cost increases
Solution Approach 1:
The patent implements a universal processor design that can dynamically adapt to different application requirements through software-controlled reconfiguration of hardware parameters. Instead of using multiple specialized processor cores (big.LITTLE architecture), a single processor type can be dynamically optimized for different workloads, achieving application versatility while significantly reducing hardware complexity and cost.
Solution Approach 2:
The invention merges the functionality of multiple specialized processor cores into a single reconfigurable processor unit. By combining high-performance and low-power capabilities in one adaptable processor, the system eliminates the need for separate hardware components, reducing manufacturing costs, device complexity, and inventory requirements while maintaining the ability to handle diverse application requirements.
Data Source
AI summary
A processor comprises an execution unit and a performance switching module coupled to the execution unit. The performance switching module includes a control unit, a clock control unit, a voltage control unit and a multi-cycle path control unit. The control unit is configured to output at least one control instruction according to a performance requirement of the processor. The clock control unit is configured to receive a clock adjustment instruction on the at least one control instruction to adjust a clock rate provided to the execution unit. The voltage control unit is configured to receive a voltage adjustment instruction of the at least one control instruction to adjust a supplied voltage provided to the execution unit. The multi-cycle path control unit is configured to receive a path adjustment instruction of the at least one control instruction to adjust a cycle number of the instruction execution cycle of the execution unit.