Dynamic Phase Equalization for Deterministic Jitter Mitigation

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Solution Overview

Problem

Communication channels face challenges in data recovery due to high frequency elements caused by deterministic jitter, which are difficult to recover until they damp out, leading to distortion and noise in electrical signals.

Innovation Solution

A dynamic phase equalization system and method that pre-drives the communication channel during bit time intervals of pre-transition bits, using a transmitter history module, detection module, driver module, and transition module to mitigate high frequency elements by pre-driving the communication channel to the second voltage of the transition bit.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data transmission rate is increased, then productivity is improved, but deterministic jitter and high frequency elements increase causing data recovery difficulty

Engineering Contradiction:
Improvedata transmission rateVSAvoiddata recovery accuracy
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary action by detecting pre-transition bits in advance and pre-driving the communication channel during their bit time intervals. This preparatory equalization action occurs before the actual transition bits are transmitted, allowing the channel to be pre-conditioned to handle upcoming high-frequency elements, thereby maintaining data recovery accuracy at higher transmission rates

Inventive Principle:
Principle #10Preliminary action

2Productivity

If transmission rate is increased to meet processing speed demands, then productivity is improved, but noise and loss in the communication channel increase

Engineering Contradiction:
Improvedata transmission rateVSAvoidnoise and loss
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent applies preliminary anti-action by implementing dynamic phase equalization that counteracts the effects of noise and loss before they severely degrade the signal. By pre-driving the channel during pre-transition bit intervals, the system proactively compensates for anticipated signal degradation, allowing higher transmission rates to be sustained despite the presence of noise and loss in the communication channel

Inventive Principle:
Principle #9Preliminary anti-action

3Speed

If high frequency elements are present in the signal, then data transmission capability is improved, but data recovery becomes difficult until high frequency elements damp out

Engineering Contradiction:
Improvesignal transition speedVSAvoiddata recovery reliability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent detects pre-transition bits and pre-drives the communication channel during their bit time intervals to equalize the channel response before the actual high-frequency transition occurs. This preliminary equalization action prepares the channel to handle the upcoming high-frequency elements, allowing faster signal transitions while maintaining data recovery reliability

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS7813447B2Apparatus, system, and method for dynamic phase equalization in a communication channel
Publication Date: 2010.10.12 LENOVO GLOBAL TECHNOLOGIES SWITZERLAND INTERNATIONAL GMBH
  • US7813447B2 patent drawing
  • US7813447B2 patent drawing
  • US7813447B2 patent drawing

AI summary

An apparatus, system, and method are disclosed for dynamic phase equalization in a communication channel. A transmitter history module stores a plurality of bits from a data stream that is transmitted through the communication channel. A transmitter detection module detects a pre-transition bit of a first value that is preceded in the data stream by at least one bit of the first value and followed by a transition bit with a second value. A driver module transmits the data stream by driving the communication channel. A transition module pre-drives the communication channel to the second voltage of the transition bit during a bit time interval of the pre-transition bit.