Dynamic Pipeline Core Parameterization for FPGA Storage Reduction

Solution Overview

Problem

The existing methods for configuring Field Programmable Gate Arrays (FPGAs) require multiple pipeline code sets for different CRC block configurations, leading to increased storage needs, complexity, and error susceptibility due to the need for separate code sets for varying data widths and signal delays.

Innovation Solution

A dynamic pipeline code set is introduced, using parameter variables like signal delay and bus width to determine the circuit configuration, allowing a single code set to implement various pipeline cores, reducing the complexity and storage requirements of the hardware description language (HDL).

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple pipeline code sets are used for different CRC block configurations, then different data widths and signal delays can be supported, but storage needs and complexity increase

Engineering Contradiction:

Improvesupport for different data widths and signal delaysVSAvoidnumber of pipeline code sets

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements a universal pipeline core design that can function with multiple CRC block configurations through parameterization. The pipeline core includes configurable parameters such as data width and signal delay that allow it to adapt to different CRC block requirements without requiring separate code sets for each configuration

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent uses parameter variables to define pipeline core characteristics such as data width and signal delay. By changing these parameters, the same pipeline core can be configured to match different CRC block configurations, eliminating the need for multiple separate code sets

Inventive Principle:

Principle #35Parameter changes

2Adaptability or versatility

If multiple pipeline code sets are used for different CRC block configurations, then different data widths and signal delays can be supported, but storage needs increase

Engineering Contradiction:

Improvesupport for different data widths and signal delaysVSAvoidstorage space for HDL code

Core Design Contradiction:

Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

The patent implements a universal pipeline core design that can function with multiple CRC block configurations through parameterization. The pipeline core includes configurable parameters such as data width and signal delay that allow it to adapt to different CRC block requirements without requiring separate code sets for each configuration

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges multiple pipeline code sets into a single parameterized code set. Instead of maintaining separate HDL code for each pipeline configuration, the invention combines all configurations into one unified code set with parameters that define the specific characteristics of each configuration

Inventive Principle:

Principle #5Merging (Combining)

3Adaptability or versatility

If multiple pipeline code sets are used for different CRC block configurations, then different data widths and signal delays can be supported, but error susceptibility increases

Engineering Contradiction:

Improvesupport for different data widths and signal delaysVSAvoiderror susceptibility during software updates

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The patent implements a universal pipeline core design that can function with multiple CRC block configurations through parameterization. The pipeline core includes configurable parameters such as data width and signal delay that allow it to adapt to different CRC block requirements without requiring separate code sets for each configuration

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent uses parameter variables to define pipeline core characteristics such as data width and signal delay. By changing these parameters, the same pipeline core can be configured to match different CRC block configurations, eliminating the need for multiple separate code sets

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS7818699B1Dynamic core pipeline

Publication Date: 2010.10.19 XILINX INC

AI summary

A circuit configuration for a pipeline core to be implemented in a programmable integrated circuit (IC) is dynamically specified by providing a single code set embodying an expanded netlist representative of a dynamic circuit configuration of the pipeline core. The code set, which includes one or more parameter variables that determine the length and width of the implemented pipeline core, is synthesized by setting the parameter variables to selected constant values to generate a reduced netlist embodying a static circuit configuration for the implemented pipeline core.