Dynamic Processing Pipeline for Mixed ISA Execution

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Solution Overview

Problem

Processing pipelines in computing systems face increased complexity and cost when accommodating code from different instruction set architectures (ISAs), particularly in efficiently storing, identifying, and executing different types of instruction code.

Innovation Solution

A micro-processing system dynamically configures its processing pipeline to execute both native and non-native ISA code by determining the code type at runtime, using different pipeline configurations that include or bypass hardware decoder and address translation stages, allowing both types of code to be stored and executed in a common memory space.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the processing pipeline is designed to handle multiple instruction set architectures (ISAs), then the system can execute different types of code, but the cost and complexity of the system greatly increase

Engineering Contradiction:

Improvecapability to execute different ISA typesVSAvoidsystem complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The processing pipeline dynamically reconfigures itself based on the detected ISA type. The system transitions from a static pipeline design to a dynamic one that adapts its configuration, enabling multiple ISA support without permanently incorporating all possible decoding mechanisms simultaneously. This reduces overall complexity while maintaining versatility.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

A single processing pipeline is designed to perform multiple functions by supporting different ISA types through dynamic configuration. The pipeline can switch between handling native ISA instructions directly and handling non-native ISA instructions through translation, making one pipeline structure universal for multiple instruction sets rather than requiring separate pipelines for each ISA.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If different decode mechanisms are used for different ISA types, then each ISA can be executed correctly, but the device complexity and cost increase

Engineering Contradiction:

Improveinstruction execution accuracyVSAvoiddecode mechanism complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

A translation mechanism acts as an intermediary for non-native ISA instructions. Instead of implementing multiple specialized decode mechanisms, the system uses a single translation layer that converts non-native instructions into native ISA instructions, which are then processed by the existing decode mechanism. This maintains execution accuracy for all ISAs while avoiding the complexity of multiple decode paths.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

Rather than having multiple specialized decode mechanisms for different ISAs, the approach is inverted: a single native decode mechanism processes all instructions, with non-native instructions first being translated into the native ISA format. This reversal simplifies the decode infrastructure while maintaining support for multiple ISAs.

Inventive Principle:

Principle #13The other way round (Inversion)

3Quantity of substance

If multiple types of instruction code are stored in a common memory space, then memory efficiency improves, but the difficulty of identifying and managing different code types increases

Engineering Contradiction:

Improvememory utilization efficiencyVSAvoidcode type identification difficulty

Core Design Contradiction:

Quantity of substanceVSDifficulty of detecting and measuring

Solution Approach 1:

The system uses metadata tags or identification markers (analogous to color coding) associated with instruction code in memory to quickly identify the ISA type. These markers enable the processor to detect and distinguish between different code types efficiently without complex analysis, maintaining both memory efficiency and easy identification.

Inventive Principle:

Principle #32Color changes

Data Source

PatentUS9563432B2Dynamic configuration of processing pipeline based on determined type of fetched instruction

Publication Date: 2017.02.07 NVIDIA CORP

AI summary

Various embodiments relating to executing different types of instruction code in a micro-processing system are provided. In one embodiment, a micro-processing system includes a memory/storage subsystem configured to store non-native instruction set architecture (ISA) code and native ISA code in a common address space, fetch logic configured to retrieve the non-native ISA code and native ISA code from the common address space, instruction type determining logic configured to determine, at runtime, whether fetched instruction code is non-native ISA code or native ISA code, and processing logic configured to execute the fetched instruction code via a first pipeline configuration in response to the instruction type determining logic determining that the fetched instruction code is non-native ISA code, and via a second pipeline configuration which is different than the first pipeline configuration, in response to the instruction type determining logic determining that the fetched instruction code is native ISA code.