Dynamic PLL Control for Low Power Processor States
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Solution Overview
Problem
Conventional power management methods for computer systems, particularly in ACPI standards, fail to efficiently control phase lock loops (PLLs) when processors enter power-saving states like C3/C4, leading to higher power consumption due to uncontrolled PLL operation during normal operation states.
Innovation Solution
A power management method and apparatus that includes a power management module coupled with a PLL and peripheral modules, which detects specific conditions in peripheral modules to direct the processor to control states that manage PLL activity, such as gating or powering down the PLL, to reduce power consumption when the system is in low power states like C4.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the processor enters the lowest power consumption state (C4) frequently, then power saving is improved, but the PLL remains uncontrolled and consumes excessive power during normal operation
Solution Approach 1:
The patent implements dynamic PLL control by introducing multiple processor power states (C0-C4) with corresponding PLL control states (S0-S4). The system dynamically transitions between these states based on actual operating conditions, allowing the PLL to be freely run during high-performance needs (C0 state) and controlled or powered down during low-power states (C3/C4), thereby resolving the contradiction between power saving and operational flexibility
Solution Approach 2:
The patent changes the operational parameters of the PLL based on processor power state. By defining different PLL control configurations for different processor states (free-running in C0, controlled in C3/C4), the system optimizes power consumption parameters without sacrificing necessary operational capabilities, directly addressing the contradiction between frequent low-state entry and PLL control efficiency
2Reliability
If the PLL is always free-running in S0 state, then operational readiness is maintained, but power consumption increases during idle periods
Solution Approach 1:
The patent segments the operational states into distinct processor power states (C0-C4) with corresponding PLL control states (S0-S4). This segmentation allows the system to maintain full PLL operation (S0 state) only when absolutely necessary for system readiness, while enabling controlled or powered-down PLL operation (S3/S4 states) during idle periods, thus resolving the contradiction between maintaining readiness and reducing power consumption
3Loss of energy
If the system enters sleeping states S1-S5 frequently, then power saving improves, but the processor cannot respond quickly to interrupts or execution requests
Solution Approach 1:
The patent implements a dynamic power management scheme where the processor can operate in low-power states (C3/C4) while maintaining faster wake-up capability compared to traditional sleeping states (S1-S5). The corresponding PLL control states (S3/S4) are designed to support quick transitions back to full operation, resolving the contradiction between power saving and response speed by providing intermediate power states that balance both requirements
Data Source
AI summary
A power management method for use in a computer system having a processor, a power management module and a phase lock loop circuit (PLL) is provided. The power management module is coupled to a plurality of peripheral modules and the computer system and the processor are capable of being operated in a working state and power saving states. The method includes the following. When the computer system is operated in the working state and the processor is entered into a lowest power consumption state among the power saving states, states of the peripheral modules are detected to determine whether a specific condition has been matched. If the specific condition is matched, the processor is directed to a control state to control the PLL according to a control state configuration.