Dynamic Polishing Gap Control for Semiconductor Wafer Geometry
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Solution Overview
Problem
Existing methods for double-side polishing of semiconductor wafers often compromise between achieving optimized geometry and high removal rate, with geometry optimization typically resulting in low throughput.
Innovation Solution
The method involves varying the polishing gap between the upper and lower polishing plates during the polishing process, starting with a larger gap for high removal rate and transitioning to a smaller gap towards the end for geometry optimization, using hard polishing pads with low compressibility and a porous matrix, and adjusting the gap through deformation of the plates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a geometry-optimizing working gap is set for polishing, then manufacturing precision is improved, but productivity deteriorates due to low removal rate
Solution Approach 1:
The polishing gap is made dynamically adjustable during the polishing process. The system transitions from a static gap configuration to a dynamic one where the gap size can be changed in stages or continuously, allowing optimization of both removal rate and geometry at different process phases
Solution Approach 2:
The polishing gap parameter is changed during the polishing process to achieve different objectives at different times. By varying the gap size, the system can optimize for high removal rate initially, then transition to geometry optimization in later stages
2Device complexity
If polishing is performed with a fixed working gap, then device complexity is reduced, but manufacturing precision deteriorates due to inability to optimize geometry
Solution Approach 1:
The polishing plate is equipped with dynamic deformation capability, allowing the working gap to be adjusted during the polishing process. This dynamic feature enables geometry optimization without requiring multiple polishing steps or complex manual interventions
Data Source
AI summary
Semiconductor wafers are polished simultaneously on both the front and the rear sides between an upper polishing plate and a lower polishing plate, each covered with a polishing pad, wherein a polishing gap (x1+x2) corresponding to a difference in the respective distances between facing surfaces of upper polishing pad and lower polishing pad which come into contact with the semiconductor wafer at the inner edge and at the outer edge of the polishing pads is changed incrementally or continuously during the polishing process.