Dynamic Power Allocation Mechanism for Integrated Circuit Components

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Solution Overview

Problem

Conventional static power-sharing mechanisms fail to efficiently prioritize power budgets for integrated circuits like CPUs and GPUs under varying load conditions, leading to undesirable latencies and software execution burdens.

Innovation Solution

Implementing dynamic power allocation mechanisms where one component acts as a master controller, adjusting its power consumption to prioritize the other component based on settings in memory, allowing components to manage power sharing independently without inter-component signaling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If centralized power management mechanisms are used to prioritize power consumption, then power allocation control is improved, but signal exchange latency and software execution burden increase

Engineering Contradiction:
Improvepower allocation controlVSAvoidsignal exchange latency
Core Design Contradiction:
Ease of operationVSLoss of time

Solution Approach 1:

The patent divides the power management system into independent segments: each integrated circuit (CPU, GPU, etc.) has its own power management controller that independently monitors and adjusts power consumption. This eliminates the need for centralized control and inter-component signaling, thereby reducing latency while maintaining effective power allocation control.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Each integrated circuit is equipped with autonomous power management capabilities, allowing components to self-regulate their power consumption based on local conditions without requiring external control signals or software intervention. This self-service approach eliminates signal exchange latency while maintaining effective power prioritization.

Inventive Principle:
Principle #25Self-service

2Device complexity

If static power-sharing mechanisms are used, then power distribution is simplified, but adaptability to varying load conditions deteriorates

Engineering Contradiction:
Improvepower distribution mechanismVSAvoidpower budget prioritization
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The patent implements dynamic power management where each integrated circuit continuously monitors its power consumption and workload conditions, automatically adjusting its power usage in real-time based on current system demands. This dynamic approach maintains simple local control mechanisms while achieving high adaptability to varying load conditions.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

Each power management controller incorporates feedback mechanisms that monitor local power consumption and workload conditions, using this information to automatically adjust power allocation decisions. This feedback-driven approach enables adaptability to changing conditions while maintaining relatively simple distributed control architecture.

Inventive Principle:
Principle #23Feedback

3Ease of operation

If inter-component signaling is implemented for power management, then coordinated power control is improved, but overhead and latency increase

Engineering Contradiction:
Improvecoordinated power controlVSAvoidsoftware execution burden
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The patent combines power management functionality directly into each integrated circuit's local controller, merging the functions of power monitoring, decision-making, and execution into a single autonomous unit. This eliminates the need for separate signaling mechanisms and software coordination layers, reducing both overhead and latency while maintaining effective coordinated control through independent local decisions.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS20260029829A1Mechanism for power sharing and allocation among device components
Publication Date: 2026.01.29 NVIDIA CORP
  • US20260029829A1 patent drawing
  • US20260029829A1 patent drawing
  • US20260029829A1 patent drawing

AI summary

Systems including a power supply and multiple chips or die, wherein settings may be configured that when applied to a first one of the chips or die configure the first chip or die to associate a power allocation limit with at least a second one of the chips or die, wherein a sum of the power allocation limit and a power consumption limit of the first chip or die exceeds a total power capacity of the power supply. The systems operate the first chip or die at a lower priority than the other chips or die for receiving operating power from the power supply, and the first chip or die is operated as a master controller of allocation of the operating power from the power supply to the first chip or die and to the other chips or die.