Dynamic Power Driven Clock Tree Synthesis
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Solution Overview
Problem
Conventional clock tree synthesis methods fail to minimize dynamic power consumption in clock distribution networks, often relying on poor proxies like cell area or number of cells, which do not accurately reduce power usage.
Innovation Solution
Selecting cells from a library based on their power ratios to construct clock trees, optimizing metrics such as dynamic power, latency, skew, and area by modifying cell sizes, and using a process that evaluates objective functions to balance these factors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional CTS methods use cell area or number of cells as proxies for power optimization, then device complexity is reduced, but dynamic power consumption is not effectively minimized
Solution Approach 1:
The patent changes the optimization parameter from cell area or cell count to power ratio (dynamic power consumption divided by capacitive load). This parameter transformation enables direct power optimization by selecting cells with lower power ratios, resolving the contradiction between simplifying the CTS process and effectively minimizing dynamic power consumption.
2Loss of energy
If cell sizes are modified to optimize power consumption, then dynamic power is reduced, but timing metrics such as clock latency and skew may deteriorate
Solution Approach 1:
The patent employs dynamic cell sizing where cell dimensions are adjusted based on local requirements in the clock tree. By modifying cell sizes adaptively rather than uniformly, the method optimizes power consumption in specific regions while maintaining timing performance in critical paths, thus resolving the contradiction between power reduction and timing reliability.
Solution Approach 2:
Different cell sizes are applied to different locations in the clock tree based on local power and timing requirements. This localized optimization allows power-efficient cells to be placed where timing is less critical while maintaining larger cells in timing-sensitive areas, resolving the contradiction between global power reduction and local timing performance.
3Loss of energy
If a predetermined number of cells with lowest power ratios are selected, then power consumption is minimized, but cell library versatility is reduced
Solution Approach 1:
Instead of selecting only the single cell with the lowest power ratio, the patent selects a predetermined number of cells with the lowest power ratios (e.g., top 3-5 cells). This partial selection maintains power optimization benefits while providing sufficient versatility to handle different clock tree configurations and timing requirements, resolving the contradiction between power minimization and library versatility.
Data Source
AI summary
Dynamic power driven clock tree synthesis is described. Some embodiments can select one or more cells from a cell library based on power ratios of cells in the cell library. The embodiments can then construct a clock tree based on the one or more cells.