Dynamic Power Reduction in Combinatorial Circuit Designs
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Solution Overview
Problem
Modern integrated circuits face increasing dynamic power consumption due to higher switching activity, operating frequency, and performance requirements, which exceeds power budgets, particularly in communications applications.
Innovation Solution
A method and system that analyze a circuit netlist to identify blocks of combinatorial circuitry with high switching activity, subdividing them into portions and relocating these portions to signal paths with sufficient delay to meet target requirements, thereby reducing dynamic power consumption by spreading switching activity over multiple clock cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If circuit performance requirements are increased (higher clock frequencies, wider signal paths), then circuit functionality and speed are improved, but dynamic power consumption increases
Solution Approach 1:
The patent segments a block of combinatorial circuitry into multiple portions and distributes them across different signal paths separated by sequential circuit elements. This segmentation reduces switching activity in any single path, thereby reducing dynamic power consumption while maintaining overall circuit functionality and performance
Solution Approach 2:
The patent introduces dynamic pipelining by selectively inserting sequential circuit elements into signal paths based on switching activity analysis. This dynamic approach allows the circuit to adapt its structure to minimize power consumption while maintaining required performance levels
2Productivity
If switching activity in combinatorial circuitry is increased to meet performance requirements, then circuit functionality is improved, but dynamic power consumption increases
Solution Approach 1:
The patent segments high switching-activity combinatorial circuitry into multiple portions distributed across different clock cycles and signal paths. This reduces the switching activity burden on any single path, lowering dynamic power consumption while preserving overall circuit functionality
Solution Approach 2:
The patent employs periodic sampling and clocking mechanisms where sequential circuit elements capture signals at specific clock cycles. This periodic action distributes switching activity across multiple clock cycles, reducing instantaneous power consumption while maintaining circuit functionality
3Use of energy by moving object
If combinatorial circuitry is subdivided and portions are moved to different signal paths, then dynamic power consumption is reduced, but circuit complexity increases
Solution Approach 1:
While segmentation increases structural complexity, the patent manages this by systematically dividing combinatorial circuitry into logical portions and placing them in standardized pipeline stages, making the complexity manageable and organized
Solution Approach 2:
The patent introduces sequential circuit elements as intermediaries between combinatorial logic portions. These intermediaries manage the complexity by providing standardized interfaces and timing control, making the overall system more manageable despite increased segmentation
Data Source
AI summary
Reducing dynamic power consumption for a circuit can include analyzing, using a processor, a netlist specifying the circuit to determine a block of combinatorial circuitry in a first signal path with at least a threshold amount of switching activity and detecting, using the processor, a second signal path coupled to the block of combinatorial circuitry by a sequential circuit element. The second signal path has a delay that meets a target signal path requirement. Using the processor, the netlist can be modified by subdividing the block of combinatorial circuitry into at least a first portion and a second portion and moving one of the portions from the first signal path to the second signal path, wherein the moving separates the first portion from the second portion by the sequential circuit element.