Dynamic Power Supply for Frequency Divider
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Solution Overview
Problem
High-speed digital logic integrated circuits face challenges in reducing power consumption due to process, temperature, and frequency variations, especially at high frequencies, making low power operation difficult.
Innovation Solution
An integrated circuit design comprising a clock generation stage, delay stage, control stage, frequency divider, and power supply regulator, where the power supplied to the frequency divider is adjusted based on the delay provided by the delay stage, allowing for dynamic power management to compensate for variations and conserve power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the integrated circuit is designed to operate correctly in all regions of the wafer including worst corners, then reliability is improved, but power consumption increases due to high current being used in all areas
Solution Approach 1:
The patent implements dynamic power management by making the power supply to the frequency divider adjustable based on delay measurements. The system transitions from a static power supply design to a dynamic one where power levels are adapted in real-time based on actual circuit performance, allowing the circuit to use lower power when operating conditions permit while maintaining reliability when needed.
Solution Approach 2:
The patent changes the power supply parameter dynamically based on delay measurements. By measuring the delay in the clock signal path and adjusting the power supply voltage accordingly, the system adapts its power consumption to match actual performance requirements, rather than operating at a fixed high power level throughout.
2Adaptability or versatility
If the integrated circuit is designed to operate over a range of temperatures and frequencies, then adaptability is improved, but power consumption increases due to high current being used during normal operation
Solution Approach 1:
The patent implements a feedback mechanism where the delay stage measures the actual delay in the clock signal path, and this measurement is used to adjust the power supply to the frequency divider. This closed-loop feedback allows the system to adapt to varying temperature and frequency conditions automatically, optimizing power consumption based on real-time performance rather than operating at fixed high power levels.
Solution Approach 2:
The system dynamically adjusts power supply levels based on measured delay characteristics, enabling it to adapt to different operating conditions (temperature and frequency variations) while consuming only the necessary amount of power for current performance requirements.
3Productivity
If the frequency divider operates at high frequency, then productivity is improved, but power consumption increases making low power operation difficult
Solution Approach 1:
The patent changes the power supply voltage parameter based on measured delay characteristics. By adjusting the power supply level to match the actual delay performance, the system can operate the frequency divider at high frequencies when needed while consuming lower power than would be required if it always operated at maximum power levels, thus resolving the contradiction between high-frequency operation and low power consumption.
Data Source
AI summary
An integrated circuit includes a clock generation stage that generates a clock signal having a clock frequency dependent on a reference signal. A delay stage generates a delayed clock signal by delaying the clock signal. A control stage generates a control signal indicative of a delay of the delayed clock signal relative to the clock signal. A frequency divider generates a divided signal by dividing a dividend signal having a dividend frequency dependent on the reference signal. A power supply regulator supplies power to the frequency divider at a first power level, which is dependent on the control signal.