Dynamic Power Limit Sharing for Processor and Memory Modules

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In traditional micro-processor based platforms, separate power domains for processors and memory modules limit system performance, especially for low-bandwidth workloads, as they do not allow for dynamic power allocation.

Innovation Solution

Expanding the power domain to include both processor and memory modules enables dynamic power limit sharing, allowing for increased processor frequency during low-bandwidth tasks by utilizing memory power headroom, thereby optimizing peak performance within a fixed total platform power budget.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If separate power domains are used for processor and memory modules, then power consumption can be controlled within budget, but system performance is limited especially for low-bandwidth workloads

Engineering Contradiction:
Improvesystem performanceVSAvoidpower allocation flexibility
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent merges separate power domains for processor and memory modules into a unified power domain, enabling dynamic power limit sharing between these components. This allows the system to allocate power flexibly based on workload requirements, thereby improving system performance without exceeding the total power budget.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent implements dynamic power limit adjustment mechanisms that allow power allocation to change in real-time based on actual workload demands. The power limits are not fixed but can be dynamically modified to optimize performance for different operational scenarios, particularly benefiting low-bandwidth workloads.

Inventive Principle:
Principle #15Dynamics

2Speed

If fixed power limits are assigned to processor and memory modules, then power budget is controlled, but processor frequency cannot be increased during low-bandwidth tasks

Engineering Contradiction:
Improveprocessor frequencyVSAvoidpower limit rigidity
Core Design Contradiction:
SpeedVSPower

Solution Approach 1:

The patent replaces fixed power limits with dynamic power limit adjustment mechanisms. The power limits for processor and memory modules can be modified in real-time based on workload characteristics, allowing the processor frequency to be increased during low-bandwidth tasks when memory power headroom is available.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the power limit parameters dynamically based on workload conditions. By monitoring workload characteristics and available power headroom, the system adjusts power limit parameters to enable higher processor frequencies when appropriate, thereby improving speed without violating power constraints.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If multiple guard bands are used to ensure power compliance, then power budget constraints are met, but system efficiency is reduced

Engineering Contradiction:
Improvesystem efficiencyVSAvoidpower budget compliance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

By merging power domains and enabling power limit sharing, the patent reduces the need for multiple conservative guard bands. The unified power domain with dynamic adjustment capabilities allows for more efficient power utilization while maintaining compliance with the total power budget, thereby improving system efficiency.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS9557804B2Dynamic power limit sharing in a platform
Publication Date: 2017.01.31 INTEL CORP
  • US9557804B2 patent drawing
  • US9557804B2 patent drawing
  • US9557804B2 patent drawing

AI summary

A method and apparatus for dynamic power limit sharing among the modules in the platform. In one embodiment of the invention, the platform comprises a processor and memory modules. By expanding the power domain to include the processor and the memory modules, dynamic sharing of the power budget of the platform between the processor and the memory modules is enabled. For low-bandwidth workloads, the dynamic sharing of the power budget offers significant opportunity for the processor to increase its frequency by using the headroom in the memory power and vice versa. This enables higher peak performance for the same total platform power budget in one embodiment of the invention.