Dynamic Power Saving Mode Controller for Computer Systems
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Solution Overview
Problem
Computer systems, even when idle, do not effectively reduce power consumption during operation, as they typically operate at fixed frequencies and voltages, leading to inefficiencies, especially in battery-powered devices where extended usage is desired.
Innovation Solution
A method and chipset implementation that classify power consumption into multiple modes, dynamically adjusting voltage supply levels and working frequencies based on system activity, allowing the computer system to automatically transition between power saving modes to minimize power usage while operating.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the computer system operates at fixed working frequency and operating voltage, then the system stability is maintained, but the power consumption cannot be reduced during working state
Solution Approach 1:
The patent implements dynamic frequency adjustment and voltage scaling mechanisms that allow the computer system to adapt its operating parameters in real-time based on workload requirements. The system transitions from fixed operational parameters to dynamic, workload-responsive parameters, enabling power consumption reduction during light workload conditions while maintaining performance during intensive tasks.
Solution Approach 2:
The patent changes the operating parameters (frequency and voltage) of the computer system components based on detected workload conditions. By implementing multiple power saving modes with different frequency-voltage combinations, the system optimizes power consumption according to actual usage patterns, resolving the contradiction between energy efficiency and system adaptability.
2Use of energy by moving object
If the computer enters G1 sleep state to reduce power consumption, then power saving is achieved, but system context is lost requiring reactivation
Solution Approach 1:
The patent segments the power management approach into multiple discrete power saving modes (PSM 0, PSM 1, PSM 2, PSM 3) with different levels of power reduction and context preservation. This segmentation allows the system to choose appropriate modes based on whether quick reactivation or maximum power saving is needed, balancing power consumption with reactivation time considerations.
Solution Approach 2:
The system performs preliminary assessment of workload conditions and user needs before transitioning to power saving modes. By predicting whether the system will be quickly reactivated or left idle, the system pre-selects appropriate power saving modes that balance context preservation with power reduction, avoiding unnecessary reactivation delays.
3Use of energy by moving object
If the computer system dynamically decreases working frequency and lowers operating voltage, then power consumption is reduced during working state, but system performance may be affected
Solution Approach 1:
The patent implements feedback mechanisms that continuously monitor system workload, temperature, and performance metrics to dynamically adjust frequency and voltage settings. This closed-loop control ensures that power saving measures are applied only when and where they can be effective, maintaining optimal performance-power consumption balance based on real-time system conditions.
Solution Approach 2:
The patent applies different frequency-voltage optimization strategies to different system components and workload types. Rather than uniformly reducing all operations, the system identifies and optimizes specific processing tasks, applying local quality adjustments that preserve overall system performance while reducing total power consumption through selective optimization.
Data Source
AI summary
A method for reducing power consumption of a computer system in a working state is provided. The computer system comprises a processor, a memory and a chipset, and the processor is connected with the chipset through a processor bus. The method comprises classifying the power saving level of the computer system into a predetermined number of power saving modes, checking at least one power saving mode transition condition to determine whether to automatically raise the power saving mode of the computer system, and raising the power saving mode of the computer system by lowering a first voltage supply level of the chipset and a second voltage supply level of the memory and decreasing a first working frequency of the processor bus and a second working frequency of the memory. The power consumption of the computer system is further reduced in comparison with a normal working state when the power saving mode of the computer system is further raised.