Dynamic Power Supply Voltage Control for Semiconductor Memory Cells
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Solution Overview
Problem
The challenge in semiconductor memory devices with flip-flop-type memory cells is achieving stable memory cell characteristics and low power consumption due to increased leak current and variations in transistor characteristics, which affect the write level and static noise margin, especially as process rules become finer.
Innovation Solution
A semiconductor memory device with a memory cell power supply circuit that dynamically controls the power supply voltage based on the arrangement of the memory cell array, transistor characteristics, and operating conditions, using a dual voltage system for read and write cycles to optimize power supply and reduce leak current impact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the power supply voltage of memory cells connected to non-selected bit lines is lowered to compensate for off-leak current, then power consumption is reduced, but the static noise margin deteriorates and data corruption becomes more likely
Solution Approach 1:
The patent applies dynamic power supply voltage control by switching between a first power supply voltage (higher) during read operations and a second power supply voltage (lower) during write operations. This dynamic adjustment allows the system to optimize power consumption during writes while maintaining adequate noise margins during reads, resolving the contradiction between energy efficiency and reliability
Solution Approach 2:
The patent changes the power supply voltage parameter based on operational mode (read vs. write). By controlling the power supply voltage to be higher during reads and lower during writes, the system adapts the electrical parameters to match operational requirements, achieving both low power consumption and maintained static noise margin
2Productivity
If a higher power supply voltage is used during write operations, then the write level is improved and write time is reduced, but power consumption increases
Solution Approach 1:
The patent implements periodic switching of power supply voltage levels synchronized with write and read operations. During write operations, a higher voltage is applied temporarily to achieve fast writing, then switched to a lower voltage during read operations to reduce power consumption. This periodic action pattern resolves the contradiction between write speed and power consumption
3Area of stationary object
If the memory cell array is designed with finer process rules to reduce area, then layout area is reduced, but transistor characteristic variations increase and stable memory cell characteristics become difficult to achieve
Solution Approach 1:
The patent applies different power supply voltage levels to different operational contexts (read vs. write) rather than using a uniform voltage. This local differentiation of electrical conditions compensates for transistor variations by providing optimized voltage levels for each operation type, maintaining stable memory cell characteristics despite process variations in scaled-down designs
Data Source
AI summary
A semiconductor memory device having a memory cell including a flip-flop; and a memory cell power supply circuit for supplying a low voltage cell power supply voltage to the memory cell. The memory cell power supply circuit supplies a cell power supply voltage in a first period and a different cell power supply voltage in a second period, a predetermined first power supply voltage in a case where the cell power supply voltage is supplied in a data read cycle and in a case where data is not written to a memory cell to which the cell power supply voltage is supplied in a write cycle, and a second power supply voltage higher than the first power supply voltage in a case where data is written to a memory cell to which the cell power supply voltage is supplied in a write cycle.