Dynamic PRBS Generator for High-Throughput LFSR Reconfiguration

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Solution Overview

Problem

Conventional Linear Feedback Shift Registers (LFSRs) become impractical for systems requiring increased throughput due to the need for multiple flip-flops to implement parallel data processing, leading to inefficiencies in generating pseudo-random bit sequences (PRBS) for testing communication channels.

Innovation Solution

A dynamic pseudo-random bit sequence generator using a dynamic linear feedback shift register (DLFSR) and XOR trees, which adjusts the number of flip-flops and data width based on requested polynomial functions, allowing for efficient generation of PRBS with varying orders and data widths without adding additional circuitry.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If LFSR is implemented in parallel to increase throughput, then productivity is improved, but device complexity increases due to the increased number of flip-flops required

Engineering Contradiction:

ImprovethroughputVSAvoidnumber of flip-flops

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent implements a dynamic LFSR where the data width and number of active flip-flops can be adjusted based on the required polynomial order. The system uses a maximum data width register and polynomial order register to dynamically configure the LFSR, allowing it to adapt between single-bit and multi-bit parallel operation modes, thereby resolving the contradiction between throughput and complexity.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The system changes operational parameters (data width and polynomial order) to optimize performance. By using configurable data width and polynomial order registers, the LFSR can be dynamically reconfigured to use only the necessary number of flip-flops for the current test requirement, reducing complexity while maintaining the ability to achieve high throughput when needed.

Inventive Principle:

Principle #35Parameter changes

2Device complexity

If conventional LFSR is used with fixed data width, then device complexity is reduced, but adaptability decreases when varying polynomial functions are required

Engineering Contradiction:

Improvecircuitry structureVSAvoidpolynomial function compatibility

Core Design Contradiction:

Device complexityVSAdaptability or versatility

Solution Approach 1:

The patent creates a universal LFSR structure that can handle multiple polynomial functions by using configurable data width and polynomial order registers. The same hardware circuitry can be reconfigured to support different polynomial orders (e.g., PRBS7, PRBS15, PRBS31) without requiring separate dedicated circuits for each polynomial, thus achieving multi-functionality with a single adaptable structure.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS11586419B2Dynamic pseudo-random bit sequence generator and methods therefor

Publication Date: 2023.02.21 ATI TECHNOLOGIES ULC

AI summary

A processing system includes a pseudo-random bit sequence (PRBS) control unit and a PRBS generator that is used to dynamically generate a PRBS from, for example, a first PRBS and a second PRBS. The PRBS generator is coupled to the PRBS control unit. The PRBS generator generates the second PRBS by dynamically adjusting from a first set of flip-flops of a master set of flip-flops that generate the first PRBS to a second set of flip-flops of the first master set of flip-flops that generate the second PRBS. The PRBS generator includes a plurality of PRBS logic engines coupled to a first PRBS multiplexer, the first PRBS multiplexer being used to select either the first PRBS or the second PRBS that is output by the PRBS generator.