Dynamic Pre-Voltage Control for Memory Cell Read Stability

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Solution Overview

Problem

The existing memory devices face challenges in maintaining accurate threshold voltage distribution over time, leading to errors in read operations due to changes in threshold voltages caused by elapsed time, operating temperature, and number of accesses, which affects the reliability and accuracy of data retrieval.

Innovation Solution

A memory device that includes a control logic system to determine and apply a pre-voltage to selected memory cells before read operations, based on parameters such as elapsed time, physical position, and operating temperature, to stabilize the threshold voltage distribution and improve read operation accuracy.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a fixed read voltage is applied to memory cells, then the circuit design is simple, but the threshold voltage distribution becomes unstable over time leading to read errors

Engineering Contradiction:
Improveread operation reliabilityVSAvoidvoltage control complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies dynamics by transitioning from a fixed read voltage to a dynamic pre-voltage that changes based on elapsed time after programming. The control logic adjusts the pre-voltage level according to the time parameter, allowing the voltage to adapt to the changing threshold voltage distribution of memory cells over time, thereby maintaining read reliability without requiring complex multi-parameter control

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements parameter changes by modifying the pre-voltage level based on the elapsed time after programming. The control logic determines different pre-voltage levels corresponding to different time intervals, changing the voltage parameter to compensate for threshold voltage drift and maintain accurate read operations

Inventive Principle:
Principle #35Parameter changes

2Stability of the object's composition

If the pre-voltage level is increased to compensate for threshold voltage drift, then the threshold voltage distribution stabilizes, but the voltage window between set and reset states may be compromised

Engineering Contradiction:
Improvethreshold voltage distribution stabilityVSAvoidvoltage window integrity
Core Design Contradiction:
Stability of the object's compositionVSReliability

Solution Approach 1:

The patent applies parameter changes by adjusting the pre-voltage level according to the elapsed time after programming. For shorter time intervals, a lower pre-voltage level is applied, while for longer time intervals, a higher pre-voltage level is used. This time-dependent parameter adjustment stabilizes the threshold voltage distribution while preserving the voltage window by avoiding excessive pre-voltage application

Inventive Principle:
Principle #35Parameter changes

3Speed

If the read operation is performed immediately after programming, then the access time is short, but the threshold voltage has not stabilized causing read errors

Engineering Contradiction:
Improveread access speedVSAvoidread operation accuracy
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent implements preliminary action by applying a pre-voltage to the selected memory cell before performing the read operation. This pre-voltage application stabilizes the threshold voltage distribution in advance, ensuring accurate read results without requiring a long delay between programming and reading, thus maintaining fast access speed while improving reliability

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12159666B2Memory device
Publication Date: 2024.12.03 SAMSUNG ELECTRONICS CO LTD
  • US12159666B2 patent drawing
  • US12159666B2 patent drawing
  • US12159666B2 patent drawing

AI summary

A memory device includes a cell region including a plurality of word lines, a plurality of bit lines, and a plurality of memory cells connected to the plurality of word lines and the plurality of bit lines disposed therein, where each of the plurality of memory cells includes a switch element and a memory element connected to each other in series between a corresponding word line and a corresponding bit line, and a peripheral circuit region including a control logic configured to, when a read command for a selected memory cell among the memory cells is received from an external controller, input a pre-voltage to the selected memory cell before reading data of the selected memory cell. The control logic is configured to determine a level of the pre-voltage with reference to an elapsed time after programming of the selected memory cell.