Dynamic Prediction Window for Sensor Timestamp Synchronization

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Solution Overview

Problem

Data acquisition between systems with different clock domains, such as sensors and processor systems, often results in incomplete or incorrect timestamps, missing, noisy, or faulty data due to clock drift and lack of timing synchronization.

Innovation Solution

Implementing a dynamically synchronized prediction window that adapts the FPGA system clock to the sensor clock domain, using interrupt requests and time offsets to filter out glitches and ensure accurate data capture within predicted windows.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If fixed time windows are used for data acquisition, then the receiving system can sample data from sensors, but clock drift between different clock domains causes incomplete or incorrect timestamps and missing data

Engineering Contradiction:
Improvedata acquisition reliabilityVSAvoidtimestamp accuracy
Core Design Contradiction:
ReliabilityVSMeasurement precision

Solution Approach 1:

The patent implements a dynamic prediction window that adapts its timing based on feedback about actual data arrival times. The window shifts and adjusts its position to account for clock drift between sensor and receiving system, allowing the system to maintain accurate timestamping despite frequency differences between clock domains.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system uses feedback mechanisms where the receiving system monitors actual data arrival times and adjusts the prediction window accordingly. This feedback loop enables the system to compensate for clock drift and maintain synchronization between different clock domains, ensuring accurate timestamp capture.

Inventive Principle:
Principle #23Feedback

2Measurement precision

If timing synchronization is implemented between sensor and receiving system, then data acquisition accuracy improves, but system complexity increases due to feedback mechanisms and clock domain management

Engineering Contradiction:
Improvetimestamp accuracyVSAvoidtiming synchronization complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The system performs preliminary actions by establishing prediction windows before actual data acquisition. These pre-calculated time windows, adjusted for expected clock drift, prepare the receiving system to accurately capture timestamps without requiring complex real-time synchronization adjustments during data acquisition.

Inventive Principle:
Principle #10Preliminary action

3Loss of time

If dynamically synchronized prediction window is implemented, then data acquisition latency is reduced, but device complexity increases due to adaptive timing mechanisms

Engineering Contradiction:
Improvedata acquisition latencyVSAvoidadaptive timing mechanism complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The dynamic prediction window continuously adapts its timing based on actual data arrival patterns, allowing the system to minimize latency by shifting the window position to optimally capture data. This dynamic adjustment eliminates the need for fixed, conservative time windows that would introduce unnecessary latency.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS20240086348A1Capturing timestamp-based data in a dynamically aligned window
Publication Date: 2024.03.14 BLUE ORIGIN MANUFACTURING LLC
  • US20240086348A1 patent drawing
  • US20240086348A1 patent drawing
  • US20240086348A1 patent drawing

AI summary

A method and system are described for data acquisition between or among two or more systems having individual clock domains, such as from a sensor system to a processor system, each system operating on its own clock domain. The sensor system, such as navigation sensors, generally output time information via various discrete signals that are generated by a clock of the sensor system. On the other hand, the processor system, such as an FPGA, may operate on a different clock. The FPGA may use predicted windows in which to monitor for the availability of sensor data, which will be timestamped for a navigation algorithm to subsequently use. Use of such predicted windows can filter unwanted data transactions, which may arise from various glitches or mis-timings between the two systems.