Dynamic Prescaler Correction for Accurate System Timer Counts
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Solution Overview
Problem
Existing systems face challenges in maintaining accurate system timer counts due to frequency drift caused by variations in temperature and voltage, leading to inconsistencies in timing channels and increased system complexity.
Innovation Solution
Implementing clock divider circuitry to divide the system clock by a pre-scaler input, counter circuitry to increment the system count, comparison circuitry to determine count differences, and controller circuitry to modify the pre-scaler input based on a threshold value, dynamically correcting timing errors by adjusting the frequency of the divided clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the system timer count is generated using a system clock without dynamic correction, then the system operation is simple, but the timing accuracy deteriorates due to frequency drift from temperature and voltage variations
Solution Approach 1:
The patent implements a feedback mechanism where the system timer count is continuously compared against a reference time source (RTC counter). The difference between these counts is fed back to dynamically adjust the pre-scaler value, creating a closed-loop system that automatically compensates for frequency drift without requiring complex external correction mechanisms
Solution Approach 2:
The patent changes the pre-scaler parameter dynamically based on the detected timing error. By adjusting the pre-scaler value according to the count difference between system timer and RTC, the system adapts to frequency variations caused by temperature and voltage changes, improving timing accuracy through parameter optimization
2Measurement precision
If the pre-scaler value is adjusted frequently to correct timing errors, then the timing accuracy is improved, but the capture and compare values in timing channels become inconsistent
Solution Approach 1:
The patent applies partial correction by adjusting the pre-scaler value incrementally rather than making large frequent changes. The correction is applied only when the count difference exceeds a threshold, and the adjustment magnitude is limited to prevent disrupting the stability of capture and compare values while still improving timing accuracy
Solution Approach 2:
The patent implements dynamic adjustment of the pre-scaler value based on real-time timing error detection. The system transitions from a static pre-scaler configuration to a dynamic one that adapts to frequency drift while maintaining stability through controlled, conditional adjustments rather than continuous changes
3Measurement precision
If a traditional time correction method is used that resets or jumps the system timer count, then the timing accuracy is improved, but discontinuities are introduced in the timer count
Solution Approach 1:
The patent prepares for potential timing errors by continuously monitoring the count difference between system timer and RTC. Instead of allowing large errors to accumulate and then making abrupt corrections, the system gradually compensates for drift through incremental pre-scaler adjustments, cushioning against future timing discrepancies while maintaining continuous operation
Solution Approach 2:
The patent converts the harmful effect of frequency drift into a beneficial correction mechanism. By detecting the timing error caused by frequency variations and using this information to dynamically adjust the pre-scaler, the system transforms the problem of frequency instability into an opportunity for self-correction, improving accuracy without introducing discontinuities
Data Source
AI summary
An example apparatus includes clock divider circuitry configured to divide a system clock by a pre-scaler input to generate a divided clock; counter circuitry configured to increment a system count based on the divided clock; comparison circuitry configured to determine a count difference between the system count and a real-time clock count; and controller circuitry configured to modify the pre-scaler input based on a comparison of the count difference to a threshold value.


